Commit f5c3fe30 authored by David Hildenbrand's avatar David Hildenbrand Committed by Andrew Morton
Browse files

xtensa/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE 

Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE by using bit 1.  This bit
should be safe to use for our usecase.

Most importantly, we can still distinguish swap PTEs from PAGE_NONE PTEs
(see pte_present()) and don't use one of the two reserved attribute masks
(1101 and 1111).  Attribute mask 1100 and 1110 now identify swap PTEs.

While at it, remove SWP_TYPE_BITS (not really helpful as it's not used in
the actual swap macros) and mask the type in __swp_entry().

Link: https://lkml.kernel.org/r/20230113171026.582290-26-david@redhat.com


Signed-off-by: default avatarDavid Hildenbrand <david@redhat.com>
Cc: Chris Zankel <chris@zankel.net>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
parent 93c0eac4

arch/xtensa/include/asm/pgtable.h

+27 −5
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ 
 *		+- - - - - - - - - - - - - - - - - - - - -+

 *   (PAGE_NONE)|    PPN    | 0 | 00 | ADW | 01 | 11 | 11 |

 *		+-----------------------------------------+

 *   swap	|     index     |   type   | 01 | 11 | 00 |

 *   swap	|     index     |   type   | 01 | 11 | e0 |

 *		+-----------------------------------------+

 *

 * For T1050 hardware and earlier the layout differs for present and (PAGE_NONE)
@@ -112,6 +112,7 @@ 
 *   RI         ring (0=privileged, 1=user, 2 and 3 are unused)

 *   CA		cache attribute: 00 bypass, 01 writeback, 10 writethrough

 *		(11 is invalid and used to mark pages that are not present)

 *   e		exclusive marker in swap PTEs

 *   w		page is writable (hw)

 *   x		page is executable (hw)

 *   index      swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB)
@@ -158,6 +159,9 @@ 
#define _PAGE_DIRTY		(1<<7)	/* software: page dirty */

#define _PAGE_ACCESSED		(1<<8)	/* software: page accessed (read) */



/* We borrow bit 1 to store the exclusive marker in swap PTEs. */

#define _PAGE_SWP_EXCLUSIVE	(1<<1)



#ifdef CONFIG_MMU



#define _PAGE_CHG_MASK	   (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
@@ -343,19 +347,37 @@ ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 
}



/*

 * Encode and decode a swap and file entry.

 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that

 * are !pte_none() && !pte_present().

 */

#define SWP_TYPE_BITS		5

#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)

#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)



#define __swp_type(entry)	(((entry).val >> 6) & 0x1f)

#define __swp_offset(entry)	((entry).val >> 11)

#define __swp_entry(type,offs)	\

	((swp_entry_t){((type) << 6) | ((offs) << 11) | \

	((swp_entry_t){(((type) & 0x1f) << 6) | ((offs) << 11) | \

	 _PAGE_CA_INVALID | _PAGE_USER})

#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })

#define __swp_entry_to_pte(x)	((pte_t) { (x).val })



#define __HAVE_ARCH_PTE_SWP_EXCLUSIVE

static inline int pte_swp_exclusive(pte_t pte)

{

	return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;

}



static inline pte_t pte_swp_mkexclusive(pte_t pte)

{

	pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;

	return pte;

}



static inline pte_t pte_swp_clear_exclusive(pte_t pte)

{

	pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;

	return pte;

}



#endif /*  !defined (__ASSEMBLY__) */