Commit f5b8bae0 authored by Junhao He's avatar Junhao He
Browse files

Revert "drivers/perf: hisi: Add support for HiSilicon H60PA and PAv3 PMU driver" 

driver inclusion
category: cleanup
bugzilla: https://gitee.com/openeuler/kernel/issues/I7VP5K


CVE: NA

----------------------------------------------------------------------

Synchronizing the mainline patches.

This reverts commit f60853f0.

Signed-off-by: default avatarJunhao He <hejunhao3@huawei.com>
parent 338c3655

drivers/perf/hisilicon/hisi_uncore_pa_pmu.c

+16 −124
Original line number Original line Diff line number Diff line
@@ -22,14 +22,9 @@ 
#define PA_TT_CTRL			0x1c08

#define PA_TT_CTRL			0x1c08

#define PA_TGTID_CTRL			0x1c14

#define PA_TGTID_CTRL			0x1c14

#define PA_SRCID_CTRL			0x1c18

#define PA_SRCID_CTRL			0x1c18

/* H32 PA interrupt registers */

#define PA_INT_MASK			0x1c70

#define PA_INT_MASK			0x1c70

#define PA_INT_STATUS			0x1c78

#define PA_INT_STATUS			0x1c78

#define PA_INT_CLEAR			0x1c7c

#define PA_INT_CLEAR			0x1c7c

/* H60 PA interrupt registers */

#define H60PA_INT_STATUS		0x1c70

#define H60PA_INT_MASK			0x1c74

/* End interrupt registers */

#define PA_EVENT_TYPE0			0x1c80

#define PA_EVENT_TYPE0			0x1c80

#define PA_PMU_VERSION			0x1cf0

#define PA_PMU_VERSION			0x1cf0

#define PA_EVENT_CNT0_L			0x1d00

#define PA_EVENT_CNT0_L			0x1d00
@@ -51,12 +46,6 @@ HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_cmd, config1, 32, 22); 
HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_msk, config1, 43, 33);

HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_msk, config1, 43, 33);

HISI_PMU_EVENT_ATTR_EXTRACTOR(tracetag_en, config1, 44, 44);

HISI_PMU_EVENT_ATTR_EXTRACTOR(tracetag_en, config1, 44, 44);





struct hisi_pa_pmu_int_regs {

	u32 mask;

	u32 clear;

	u32 status;

};



static void hisi_pa_pmu_enable_tracetag(struct perf_event *event)

static void hisi_pa_pmu_enable_tracetag(struct perf_event *event)

{

{

	struct hisi_pmu *pa_pmu = to_hisi_pmu(event->pmu);

	struct hisi_pmu *pa_pmu = to_hisi_pmu(event->pmu);
@@ -230,51 +219,44 @@ static void hisi_pa_pmu_disable_counter(struct hisi_pmu *pa_pmu, 
static void hisi_pa_pmu_enable_counter_int(struct hisi_pmu *pa_pmu,

static void hisi_pa_pmu_enable_counter_int(struct hisi_pmu *pa_pmu,

					   struct hw_perf_event *hwc)

					   struct hw_perf_event *hwc)

{

{

	struct hisi_pa_pmu_int_regs *regs = pa_pmu->dev_info->present;

	u32 val;

	u32 val;





	/* Write 0 to enable interrupt */

	/* Write 0 to enable interrupt */

	val = readl(pa_pmu->base + regs->mask);

	val = readl(pa_pmu->base + PA_INT_MASK);

	val &= ~(1 << hwc->idx);

	val &= ~(1 << hwc->idx);

	writel(val, pa_pmu->base + regs->mask);

	writel(val, pa_pmu->base + PA_INT_MASK);

}

}





static void hisi_pa_pmu_disable_counter_int(struct hisi_pmu *pa_pmu,

static void hisi_pa_pmu_disable_counter_int(struct hisi_pmu *pa_pmu,

					    struct hw_perf_event *hwc)

					    struct hw_perf_event *hwc)

{

{

	struct hisi_pa_pmu_int_regs *regs = pa_pmu->dev_info->present;

	u32 val;

	u32 val;





	/* Write 1 to mask interrupt */

	/* Write 1 to mask interrupt */

	val = readl(pa_pmu->base + regs->mask);

	val = readl(pa_pmu->base + PA_INT_MASK);

	val |= 1 << hwc->idx;

	val |= 1 << hwc->idx;

	writel(val, pa_pmu->base + regs->mask);

	writel(val, pa_pmu->base + PA_INT_MASK);

}

}





static u32 hisi_pa_pmu_get_int_status(struct hisi_pmu *pa_pmu)

static u32 hisi_pa_pmu_get_int_status(struct hisi_pmu *pa_pmu)

{

{

	struct hisi_pa_pmu_int_regs *regs = pa_pmu->dev_info->present;

	return readl(pa_pmu->base + PA_INT_STATUS);



	return readl(pa_pmu->base + regs->status);

}

}





static void hisi_pa_pmu_clear_int_status(struct hisi_pmu *pa_pmu, int idx)

static void hisi_pa_pmu_clear_int_status(struct hisi_pmu *pa_pmu, int idx)

{

{

	struct hisi_pa_pmu_int_regs *regs = pa_pmu->dev_info->present;

	writel(1 << idx, pa_pmu->base + PA_INT_CLEAR);



	writel(1 << idx, pa_pmu->base + regs->clear);

}

}





static const struct acpi_device_id hisi_pa_pmu_acpi_match[] = {

	{ "HISI0273", },

	{}

};

MODULE_DEVICE_TABLE(acpi, hisi_pa_pmu_acpi_match);



static int hisi_pa_pmu_init_data(struct platform_device *pdev,

static int hisi_pa_pmu_init_data(struct platform_device *pdev,

				   struct hisi_pmu *pa_pmu)

				   struct hisi_pmu *pa_pmu)

{

{

	const struct hisi_pmu_dev_info *pa_pmu_info;

	int idx;



	pa_pmu_info = device_get_match_data(&pdev->dev);

	if (!pa_pmu_info)

		return -ENODEV;



	/*

	/*

	 * As PA PMU is in a SICL, use the SICL_ID and the index ID

	 * As PA PMU is in a SICL, use the SICL_ID and the index ID

	 * to identify the PA PMU.

	 * to identify the PA PMU.
@@ -302,11 +284,6 @@ static int hisi_pa_pmu_init_data(struct platform_device *pdev, 




	pa_pmu->identifier = readl(pa_pmu->base + PA_PMU_VERSION);

	pa_pmu->identifier = readl(pa_pmu->base + PA_PMU_VERSION);





	idx = hisi_uncore_pmu_ver2idx(pa_pmu);

	pa_pmu->dev_info = &pa_pmu_info[idx];

	if (!pa_pmu->dev_info || !pa_pmu->dev_info->name)

		return -EINVAL;



	return 0;

	return 0;

}

}
@@ -337,32 +314,6 @@ static const struct attribute_group hisi_pa_pmu_v2_events_group = { 
	.attrs = hisi_pa_pmu_v2_events_attr,

	.attrs = hisi_pa_pmu_v2_events_attr,

};

};





static struct attribute *hisi_pa_pmu_v3_events_attr[] = {

	HISI_PMU_EVENT_ATTR(tx_req,	0x0),

	HISI_PMU_EVENT_ATTR(tx_dat,	0x1),

	HISI_PMU_EVENT_ATTR(tx_snp,	0x2),

	HISI_PMU_EVENT_ATTR(rx_req,	0x7),

	HISI_PMU_EVENT_ATTR(rx_dat,	0x8),

	HISI_PMU_EVENT_ATTR(rx_snp,	0x9),

	NULL

};



static const struct attribute_group hisi_pa_pmu_v3_events_group = {

	.name = "events",

	.attrs = hisi_pa_pmu_v3_events_attr,

};



static struct attribute *hisi_h60pa_pmu_events_attr[] = {

	HISI_PMU_EVENT_ATTR(rx_flit,	0x50),

	HISI_PMU_EVENT_ATTR(tx_flit,	0x65),

	NULL

};



static const struct attribute_group hisi_h60pa_pmu_events_group = {

	.name = "events",

	.attrs = hisi_h60pa_pmu_events_attr,

};



static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);

static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);





static struct attribute *hisi_pa_pmu_cpumask_attrs[] = {

static struct attribute *hisi_pa_pmu_cpumask_attrs[] = {
@@ -382,7 +333,7 @@ static struct attribute *hisi_pa_pmu_identifier_attrs[] = { 
	NULL

	NULL

};

};





static const struct attribute_group hisi_pa_pmu_identifier_group = {

static struct attribute_group hisi_pa_pmu_identifier_group = {

	.attrs = hisi_pa_pmu_identifier_attrs,

	.attrs = hisi_pa_pmu_identifier_attrs,

};

};
@@ -394,57 +345,6 @@ static const struct attribute_group *hisi_pa_pmu_v2_attr_groups[] = { 
	NULL

	NULL

};

};





static const struct attribute_group *hisi_pa_pmu_v3_attr_groups[] = {

	&hisi_pa_pmu_v2_format_group,

	&hisi_pa_pmu_v3_events_group,

	&hisi_pa_pmu_cpumask_attr_group,

	&hisi_pa_pmu_identifier_group,

	NULL

};



static struct hisi_pa_pmu_int_regs hisi_pa_pmu_regs = {

	.mask = PA_INT_MASK,

	.clear = PA_INT_CLEAR,

	.status = PA_INT_STATUS,

};



static const struct hisi_pmu_dev_info hisi_h32pa[] = {

	[1] = {

		.name = "pa",

		.attr_groups = hisi_pa_pmu_v2_attr_groups,

		.present = &hisi_pa_pmu_regs,

	},

	[2] = {

		.name = "pa",

		.attr_groups = hisi_pa_pmu_v3_attr_groups,

		.present = &hisi_pa_pmu_regs,

	},

	{}

};



static const struct attribute_group *hisi_h60pa_pmu_attr_groups[] = {

	&hisi_pa_pmu_v2_format_group,

	&hisi_h60pa_pmu_events_group,

	&hisi_pa_pmu_cpumask_attr_group,

	&hisi_pa_pmu_identifier_group,

	NULL

};



static struct hisi_pa_pmu_int_regs hisi_h60pa_pmu_regs = {

	.mask = H60PA_INT_MASK,

	.clear = H60PA_INT_STATUS, /* Clear on write */

	.status = H60PA_INT_STATUS,

};



static const struct hisi_pmu_dev_info hisi_h60pa[] = {

	[1] = {

		.name = "h60pa",

		.attr_groups = hisi_h60pa_pmu_attr_groups,

		.present = &hisi_h60pa_pmu_regs,

	},

	{}

};



static const struct hisi_uncore_ops hisi_uncore_pa_ops = {

static const struct hisi_uncore_ops hisi_uncore_pa_ops = {

	.write_evtype		= hisi_pa_pmu_write_evtype,

	.write_evtype		= hisi_pa_pmu_write_evtype,

	.get_event_idx		= hisi_uncore_pmu_get_event_idx,

	.get_event_idx		= hisi_uncore_pmu_get_event_idx,
@@ -475,7 +375,7 @@ static int hisi_pa_pmu_dev_probe(struct platform_device *pdev, 
	if (ret)

	if (ret)

		return ret;

		return ret;





	pa_pmu->pmu_events.attr_groups = pa_pmu->dev_info->attr_groups;

	pa_pmu->pmu_events.attr_groups = hisi_pa_pmu_v2_attr_groups;

	pa_pmu->num_counters = PA_NR_COUNTERS;

	pa_pmu->num_counters = PA_NR_COUNTERS;

	pa_pmu->ops = &hisi_uncore_pa_ops;

	pa_pmu->ops = &hisi_uncore_pa_ops;

	pa_pmu->check_event = 0xB0;

	pa_pmu->check_event = 0xB0;
@@ -500,9 +400,8 @@ static int hisi_pa_pmu_probe(struct platform_device *pdev) 
	if (ret)

	if (ret)

		return ret;

		return ret;





	name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sicl%d_%s%u",

	name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sicl%u_pa%u",

			      pa_pmu->sicl_id, pa_pmu->dev_info->name,

			      pa_pmu->sicl_id, pa_pmu->index_id);

			      pa_pmu->index_id);

	if (!name)

	if (!name)

		return -ENOMEM;

		return -ENOMEM;
@@ -536,13 +435,6 @@ static int hisi_pa_pmu_remove(struct platform_device *pdev) 
	return 0;

	return 0;

}

}





static const struct acpi_device_id hisi_pa_pmu_acpi_match[] = {

	{ "HISI0273", (kernel_ulong_t)hisi_h32pa },

	{ "HISI0274", (kernel_ulong_t)hisi_h60pa },

	{}

};

MODULE_DEVICE_TABLE(acpi, hisi_pa_pmu_acpi_match);



static struct platform_driver hisi_pa_pmu_driver = {

static struct platform_driver hisi_pa_pmu_driver = {

	.driver = {

	.driver = {

		.name = "hisi_pa_pmu",

		.name = "hisi_pa_pmu",

drivers/perf/hisilicon/hisi_uncore_pmu.h

+2 −34
Original line number Original line Diff line number Diff line
@@ -23,6 +23,7 @@ 
#undef pr_fmt

#undef pr_fmt

#define pr_fmt(fmt)     "hisi_pmu: " fmt

#define pr_fmt(fmt)     "hisi_pmu: " fmt





#define HISI_PMU_V2		0x30

#define HISI_MAX_COUNTERS 0x10

#define HISI_MAX_COUNTERS 0x10

#define to_hisi_pmu(p)	(container_of(p, struct hisi_pmu, pmu))

#define to_hisi_pmu(p)	(container_of(p, struct hisi_pmu, pmu))
@@ -42,13 +43,6 @@ 
		return FIELD_GET(GENMASK_ULL(hi, lo), event->attr.config);  \

		return FIELD_GET(GENMASK_ULL(hi, lo), event->attr.config);  \

	}

	}





enum hisi_pmu_version {

	HISI_PMU_V1,

	HISI_PMU_V2 = 0x30,

	HISI_PMU_V3 = 0x40,

	HISI_PMU_MAX

};



struct hisi_pmu;

struct hisi_pmu;





struct hisi_uncore_ops {

struct hisi_uncore_ops {
@@ -68,13 +62,6 @@ struct hisi_uncore_ops { 
	void (*disable_filter)(struct perf_event *event);

	void (*disable_filter)(struct perf_event *event);

};

};





/* Describes the HISI PMU chip features information */

struct hisi_pmu_dev_info {

	const char *name;

	const struct attribute_group **attr_groups;

	void *present;

};



struct hisi_pmu_hwevents {

struct hisi_pmu_hwevents {

	struct perf_event *hw_events[HISI_MAX_COUNTERS];

	struct perf_event *hw_events[HISI_MAX_COUNTERS];

	DECLARE_BITMAP(used_mask, HISI_MAX_COUNTERS);

	DECLARE_BITMAP(used_mask, HISI_MAX_COUNTERS);
@@ -85,7 +72,6 @@ struct hisi_pmu_hwevents { 
struct hisi_pmu {

struct hisi_pmu {

	struct pmu pmu;

	struct pmu pmu;

	const struct hisi_uncore_ops *ops;

	const struct hisi_uncore_ops *ops;

	const struct hisi_pmu_dev_info *dev_info;

	struct hisi_pmu_hwevents pmu_events;

	struct hisi_pmu_hwevents pmu_events;

	/* associated_cpus: All CPUs associated with the PMU */

	/* associated_cpus: All CPUs associated with the PMU */

	cpumask_t associated_cpus;

	cpumask_t associated_cpus;
@@ -106,7 +92,7 @@ struct hisi_pmu { 
	int counter_bits;

	int counter_bits;

	/* check event code range */

	/* check event code range */

	int check_event;

	int check_event;

	enum hisi_pmu_version identifier;

	u32 identifier;

};

};





int hisi_uncore_pmu_get_event_idx(struct perf_event *event);

int hisi_uncore_pmu_get_event_idx(struct perf_event *event);
@@ -136,22 +122,4 @@ int hisi_uncore_pmu_init_irq(struct hisi_pmu *hisi_pmu, 
			     struct platform_device *pdev);

			     struct platform_device *pdev);





void hisi_pmu_init(struct hisi_pmu *hisi_pmu, struct module *module);

void hisi_pmu_init(struct hisi_pmu *hisi_pmu, struct module *module);



int hisi_uncore_pmu_ver2idx(struct hisi_pmu *pmu)

{

	int idx;



	switch (pmu->identifier) {

	case HISI_PMU_V1:

		idx = 0; break;

	case HISI_PMU_V2:

		idx = 1; break;

	case HISI_PMU_V3:

	/* When running on later version, returns the largest supported version */

	default:

		idx = 2;

	}



	return idx;

}

#endif /* __HISI_UNCORE_PMU_H__ */
 
#endif /* __HISI_UNCORE_PMU_H__ */