Commit f59464e2 authored by Yevgeny Kliteynik's avatar Yevgeny Kliteynik Committed by Saeed Mahameed
Browse files

net/mlx5: DR, Add support for matching on geneve_tlv_option_0_exist field 



Match on geneve_tlv_option_0_exist field on devices that support STEv1.

Signed-off-by: default avatarMuhammad Sammar <muhammads@nvidia.com>
Signed-off-by: default avatarYevgeny Kliteynik <kliteyn@nvidia.com>
parent 09753bab

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_cmd.c

+7 −0
Original line number Diff line number Diff line
@@ -132,6 +132,13 @@ int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev, 


	caps->isolate_vl_tc = MLX5_CAP_GEN(mdev, isolate_vl_tc_new);



	/* geneve_tlv_option_0_exist is the indication of

	 * STE support for lookup type flex_parser_ok

	 */

	caps->flex_parser_ok_bits_supp =

		MLX5_CAP_FLOWTABLE(mdev,

				   flow_table_properties_nic_receive.ft_field_support.geneve_tlv_option_0_exist);



	if (caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V4_ENABLED) {

		caps->flex_parser_id_icmp_dw0 = MLX5_CAP_GEN(mdev, flex_parser_id_icmp_dw0);

		caps->flex_parser_id_icmp_dw1 = MLX5_CAP_GEN(mdev, flex_parser_id_icmp_dw1);

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c

+17 −0
Original line number Diff line number Diff line
@@ -140,6 +140,19 @@ static bool dr_mask_is_tnl_geneve_tlv_opt(struct mlx5dr_match_misc3 *misc3) 
	return misc3->geneve_tlv_option_0_data;

}



static bool

dr_matcher_supp_flex_parser_ok(struct mlx5dr_cmd_caps *caps)

{

	return caps->flex_parser_ok_bits_supp;

}



static bool dr_mask_is_tnl_geneve_tlv_opt_exist_set(struct mlx5dr_match_misc *misc,

						    struct mlx5dr_domain *dmn)

{

	return dr_matcher_supp_flex_parser_ok(&dmn->info.caps) &&

	       misc->geneve_tlv_option_0_exist;

}



static bool

dr_matcher_supp_tnl_geneve(struct mlx5dr_cmd_caps *caps)

{
@@ -521,6 +534,10 @@ static int dr_matcher_set_ste_builders(struct mlx5dr_matcher *matcher, 
				mlx5dr_ste_build_tnl_geneve_tlv_opt(ste_ctx, &sb[idx++],

								    &mask, &dmn->info.caps,

								    inner, rx);

			if (dr_mask_is_tnl_geneve_tlv_opt_exist_set(&mask.misc, dmn))

				mlx5dr_ste_build_tnl_geneve_tlv_opt_exist(ste_ctx, &sb[idx++],

									  &mask, &dmn->info.caps,

									  inner, rx);

		} else if (dr_mask_is_tnl_gtpu_any(&mask, dmn)) {

			if (dr_mask_is_tnl_gtpu_flex_parser_0(&mask, dmn))

				mlx5dr_ste_build_tnl_gtpu_flex_parser_0(ste_ctx, &sb[idx++],

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c

+17 −0
Original line number Diff line number Diff line
@@ -719,6 +719,8 @@ static void dr_ste_copy_mask_misc(char *mask, struct mlx5dr_match_misc *spec, bo 
	spec->vxlan_vni = IFC_GET_CLR(fte_match_set_misc, mask, vxlan_vni, clr);



	spec->geneve_vni = IFC_GET_CLR(fte_match_set_misc, mask, geneve_vni, clr);

	spec->geneve_tlv_option_0_exist =

		IFC_GET_CLR(fte_match_set_misc, mask, geneve_tlv_option_0_exist, clr);

	spec->geneve_oam = IFC_GET_CLR(fte_match_set_misc, mask, geneve_oam, clr);



	spec->outer_ipv6_flow_label =
@@ -1214,6 +1216,21 @@ void mlx5dr_ste_build_tnl_geneve_tlv_opt(struct mlx5dr_ste_ctx *ste_ctx, 
	ste_ctx->build_tnl_geneve_tlv_opt_init(sb, mask);

}



void mlx5dr_ste_build_tnl_geneve_tlv_opt_exist(struct mlx5dr_ste_ctx *ste_ctx,

					       struct mlx5dr_ste_build *sb,

					       struct mlx5dr_match_param *mask,

					       struct mlx5dr_cmd_caps *caps,

					       bool inner, bool rx)

{

	if (!ste_ctx->build_tnl_geneve_tlv_opt_exist_init)

		return;



	sb->rx = rx;

	sb->caps = caps;

	sb->inner = inner;

	ste_ctx->build_tnl_geneve_tlv_opt_exist_init(sb, mask);

}



void mlx5dr_ste_build_tnl_gtpu(struct mlx5dr_ste_ctx *ste_ctx,

			       struct mlx5dr_ste_build *sb,

			       struct mlx5dr_match_param *mask,

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h

+1 −0
Original line number Diff line number Diff line
@@ -135,6 +135,7 @@ struct mlx5dr_ste_ctx { 
	void DR_STE_CTX_BUILDER(tnl_vxlan_gpe);

	void DR_STE_CTX_BUILDER(tnl_geneve);

	void DR_STE_CTX_BUILDER(tnl_geneve_tlv_opt);

	void DR_STE_CTX_BUILDER(tnl_geneve_tlv_opt_exist);

	void DR_STE_CTX_BUILDER(register_0);

	void DR_STE_CTX_BUILDER(register_1);

	void DR_STE_CTX_BUILDER(src_gvmi_qpn);

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c

+28 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ enum { 
	DR_STE_V1_LU_TYPE_ETHL3_IPV4_MISC_I		= 0x000f,

	DR_STE_V1_LU_TYPE_STEERING_REGISTERS_0		= 0x010f,

	DR_STE_V1_LU_TYPE_STEERING_REGISTERS_1		= 0x0110,

	DR_STE_V1_LU_TYPE_FLEX_PARSER_OK		= 0x0011,

	DR_STE_V1_LU_TYPE_FLEX_PARSER_0			= 0x0111,

	DR_STE_V1_LU_TYPE_FLEX_PARSER_1			= 0x0112,

	DR_STE_V1_LU_TYPE_ETHL4_MISC_O			= 0x0113,
@@ -1942,6 +1943,32 @@ dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init(struct mlx5dr_ste_build *sb, 
	sb->ste_build_tag_func = &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_tag;

}



static int

dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_tag(struct mlx5dr_match_param *value,

							 struct mlx5dr_ste_build *sb,

							 uint8_t *tag)

{

	u8 parser_id = sb->caps->flex_parser_id_geneve_tlv_option_0;

	struct mlx5dr_match_misc *misc = &value->misc;



	if (misc->geneve_tlv_option_0_exist) {

		MLX5_SET(ste_flex_parser_ok, tag, flex_parsers_ok, 1 << parser_id);

		misc->geneve_tlv_option_0_exist = 0;

	}



	return 0;

}



static void

dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init(struct mlx5dr_ste_build *sb,

							  struct mlx5dr_match_param *mask)

{

	sb->lu_type = DR_STE_V1_LU_TYPE_FLEX_PARSER_OK;

	dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_tag(mask, sb, sb->bit_mask);

	sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);

	sb->ste_build_tag_func = &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_tag;

}



static int dr_ste_v1_build_flex_parser_tnl_gtpu_tag(struct mlx5dr_match_param *value,

						    struct mlx5dr_ste_build *sb,

						    u8 *tag)
@@ -2041,6 +2068,7 @@ struct mlx5dr_ste_ctx ste_ctx_v1 = { 
	.build_tnl_vxlan_gpe_init	= &dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init,

	.build_tnl_geneve_init		= &dr_ste_v1_build_flex_parser_tnl_geneve_init,

	.build_tnl_geneve_tlv_opt_init	= &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init,

	.build_tnl_geneve_tlv_opt_exist_init = &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init,

	.build_register_0_init		= &dr_ste_v1_build_register_0_init,

	.build_register_1_init		= &dr_ste_v1_build_register_1_init,

	.build_src_gvmi_qpn_init	= &dr_ste_v1_build_src_gvmi_qpn_init,