Commit f5596657 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-next-2021-07-08-1' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Some fixes for rc1 that came in the past weeks, mainly a bunch of
  amdgpu fixes, some i915 and the rest are misc around the place. I'm
  sending this a bit early so some more stuff may show up, but I'll
  probably take tomorrow off.

  dma-buf:
   - doc fixes

  amdgpu:
   - Misc Navi fixes
   - Powergating fix
   - Yellow Carp updates
   - Beige Goby updates
   - S0ix fix
   - Revert overlay validation fix
   - GPU reset fix for DC
   - PPC64 fix
   - Add new dimgrey cavefish DID
   - RAS fix
   - TTM fixes

  amdkfd:
   - SVM fixes

  radeon:
   - Fix missing drm_gem_object_put in error path
   - NULL ptr deref fix

  i915:
   - display DP VSC fix
   - DG1 display fix
   - IRQ fixes
   - IRQ demidlayering

  gma500:
   - bo leaks in error paths fixed"

* tag 'drm-next-2021-07-08-1' of git://anongit.freedesktop.org/drm/drm: (52 commits)
  drm/i915: Drop all references to DRM IRQ midlayer
  drm/i915: Use the correct IRQ during resume
  drm/i915/display/dg1: Correctly map DPLLs during state readout
  drm/i915/display: Do not zero past infoframes.vsc
  drm/amdgpu: Conditionally reset SDMA RAS error counts
  drm/amdkfd: Maintain svm_bo reference in page->zone_device_data
  drm/amdkfd: add invalid pages debug at vram migration
  drm/amdkfd: skip migration for pages already in VRAM
  drm/amdkfd: skip invalid pages during migrations
  drm/amdkfd: classify and map mixed svm range pages in GPU
  drm/amdkfd: use hmm range fault to get both domain pfns
  drm/amdgpu: get owner ref in validate and map
  drm/amdkfd: set owner ref to svm range prefault
  drm/amdkfd: add owner ref param to get hmm pages
  drm/amdkfd: device pgmap owner at the svm migrate init
  drm/amdkfd: inc counter on child ranges with xnack off
  drm/amd/display: Extend DMUB diagnostic logging to DCN3.1
  drm/amdgpu: Update NV SIMD-per-CU to 2
  drm/amdgpu: add new dimgrey cavefish DID
  drm/amd/pm: skip PrepareMp1ForUnload message in s0ix
  ...
parents 8c1bfd74 21c355b0

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+37 −0
Original line number Diff line number Diff line
@@ -1369,6 +1369,38 @@ static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) 
	adev->pm.smu_prv_buffer_size = 0;

}



static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)

{

	if (!(adev->flags & AMD_IS_APU) ||

	    adev->asic_type < CHIP_RAVEN)

		return 0;



	switch (adev->asic_type) {

	case CHIP_RAVEN:

		if (adev->pdev->device == 0x15dd)

			adev->apu_flags |= AMD_APU_IS_RAVEN;

		if (adev->pdev->device == 0x15d8)

			adev->apu_flags |= AMD_APU_IS_PICASSO;

		break;

	case CHIP_RENOIR:

		if ((adev->pdev->device == 0x1636) ||

		    (adev->pdev->device == 0x164c))

			adev->apu_flags |= AMD_APU_IS_RENOIR;

		else

			adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;

		break;

	case CHIP_VANGOGH:

		adev->apu_flags |= AMD_APU_IS_VANGOGH;

		break;

	case CHIP_YELLOW_CARP:

		break;

	default:

		return -EINVAL;

	}



	return 0;

}



/**

 * amdgpu_device_check_arguments - validate module params

 *
@@ -3386,6 +3418,10 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	mutex_init(&adev->psp.mutex);

	mutex_init(&adev->notifier_lock);



	r = amdgpu_device_init_apu_flags(adev);

	if (r)

		return r;



	r = amdgpu_device_check_arguments(adev);

	if (r)

		return r;
@@ -4304,6 +4340,7 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) 
		case CHIP_SIENNA_CICHLID:

		case CHIP_NAVY_FLOUNDER:

		case CHIP_DIMGREY_CAVEFISH:

		case CHIP_BEIGE_GOBY:

		case CHIP_VANGOGH:

		case CHIP_ALDEBARAN:

			break;

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −0
Original line number Diff line number Diff line
@@ -160,6 +160,7 @@ int amdgpu_smu_pptable_id = -1; 
 *     highest. That helps saving some idle power.

 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default

 * PSR (bit 3) disabled by default

 * EDP NO POWER SEQUENCING (bit 4) disabled by default

 */

uint amdgpu_dc_feature_mask = 2;

uint amdgpu_dc_debug_mask;
@@ -1198,6 +1199,7 @@ static const struct pci_device_id pciidlist[] = { 
	{0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},



	/* Aldebaran */

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+1 −0
Original line number Diff line number Diff line
@@ -562,6 +562,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 
	case CHIP_NAVI14:

	case CHIP_NAVI12:

	case CHIP_VANGOGH:

	case CHIP_YELLOW_CARP:

		/* Don't enable it by default yet.

		 */

		if (amdgpu_tmz < 1) {

drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c

+2 −1
Original line number Diff line number Diff line
@@ -160,7 +160,7 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, 
			       struct mm_struct *mm, struct page **pages,

			       uint64_t start, uint64_t npages,

			       struct hmm_range **phmm_range, bool readonly,

			       bool mmap_locked)

			       bool mmap_locked, void *owner)

{

	struct hmm_range *hmm_range;

	unsigned long timeout;
@@ -185,6 +185,7 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, 
	hmm_range->hmm_pfns = pfns;

	hmm_range->start = start;

	hmm_range->end = start + npages * PAGE_SIZE;

	hmm_range->dev_private_owner = owner;



	/* Assuming 512MB takes maxmium 1 second to fault page address */

	timeout = max(npages >> 17, 1ULL) * HMM_RANGE_DEFAULT_TIMEOUT;

drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, 
			       struct mm_struct *mm, struct page **pages,

			       uint64_t start, uint64_t npages,

			       struct hmm_range **phmm_range, bool readonly,

			       bool mmap_locked);

			       bool mmap_locked, void *owner);

int amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range);



#if defined(CONFIG_HMM_MIRROR)