Commit f537ee7f authored by Shenwei Wang's avatar Shenwei Wang Committed by Shawn Guo
Browse files

arm64: dts: freescale: add i.MX8DXL SoC support 



i.MX8DXL is a device targeting the automotive and industrial market
segments. The chip is designed to achieve both high performance and
low power consumption. It has a dual (2x) Cortex-A35 processor.

This patch adds the basic support for i.MX8DXL SoC.

Signed-off-by: default avatarShenwei Wang <shenwei.wang@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 41d5ceff

arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi

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// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright 2019~2020, 2022 NXP

 */



&audio_ipg_clk {

	clock-frequency = <160000000>;

};



&dma_ipg_clk {

	clock-frequency = <160000000>;

};



&i2c0 {

	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;

};



&i2c1 {

	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;

};



&i2c2 {

	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

	interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;

};



&i2c3 {

	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;

};



&lpuart0 {

	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

	interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;

};



&lpuart1 {

	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

	interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;

};



&lpuart2 {

	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

	interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;

};



&lpuart3 {

	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

	interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;

};

arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi

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// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright 2019~2020, 2022 NXP

 */



/delete-node/ &enet1_lpcg;

/delete-node/ &fec2;



&conn_subsys {

	conn_enet0_root_clk: clock-conn-enet0-root {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <250000000>;

		clock-output-names = "conn_enet0_root_clk";

	};



	eqos: ethernet@5b050000 {

		compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";

		reg = <0x5b050000 0x10000>;

		interrupt-parent = <&gic>;

		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "eth_wake_irq", "macirq";

		clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,

			 <&eqos_lpcg IMX_LPCG_CLK_6>,

			 <&eqos_lpcg IMX_LPCG_CLK_0>,

			 <&eqos_lpcg IMX_LPCG_CLK_5>,

			 <&eqos_lpcg IMX_LPCG_CLK_2>;

		clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";

		assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <125000000>;

		power-domains = <&pd IMX_SC_R_ENET_1>;

		status = "disabled";

	};



	usbotg2: usb@5b0e0000 {

		compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";

		reg = <0x5b0e0000 0x200>;

		interrupt-parent = <&gic>;

		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;

		fsl,usbphy = <&usbphy2>;

		fsl,usbmisc = <&usbmisc2 0>;

		/*

		 * usbotg1 and usbotg2 share one clcok.

		 * scu firmware disables the access to the clock and keeps

		 * it always on in case other core (M4) uses one of these.

		 */

		clocks = <&clk_dummy>;

		ahb-burst-config = <0x0>;

		tx-burst-size-dword = <0x10>;

		rx-burst-size-dword = <0x10>;

		#stream-id-cells = <1>;

		power-domains = <&pd IMX_SC_R_USB_1>;

		status = "disabled";



		clk_dummy: clock-dummy {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <0>;

			clock-output-names = "clk_dummy";

		};

	};



	usbmisc2: usbmisc@5b0e0200 {

		#index-cells = <1>;

		compatible = "fsl,imx7ulp-usbmisc";

		reg = <0x5b0e0200 0x200>;

	};



	usbphy2: usbphy@0x5b110000 {

		compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";

		reg = <0x5b110000 0x1000>;

		clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>;

		power-domains = <&pd IMX_SC_R_USB_1_PHY>;

		status = "disabled";

	};



	eqos_lpcg: clock-controller@5b240000 {

		compatible = "fsl,imx8qxp-lpcg";

		reg = <0x5b240000 0x10000>;

		#clock-cells = <1>;

		clocks = <&conn_enet0_root_clk>,

			 <&conn_axi_clk>,

			 <&conn_axi_clk>,

			 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,

			 <&conn_ipg_clk>;

		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>,

				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,

				<IMX_LPCG_CLK_6>;

		clock-output-names = "eqos_ptp",

				     "eqos_mem_clk",

				     "eqos_aclk",

				     "eqos_clk",

				     "eqos_csr_clk";

		power-domains = <&pd IMX_SC_R_ENET_1>;

	};



	usb2_2_lpcg: clock-controller@5b280000 {

		compatible = "fsl,imx8qxp-lpcg";

		reg = <0x5b280000 0x10000>;

		#clock-cells = <1>;

		clock-indices = <IMX_LPCG_CLK_7>;

		clocks = <&conn_ipg_clk>;

		clock-output-names = "usboh3_2_phy_ipg_clk";

		power-domains = <&pd IMX_SC_R_USB_1_PHY>;

	};



};



&enet0_lpcg {

	clocks = <&conn_enet0_root_clk>,

		 <&conn_enet0_root_clk>,

		 <&conn_axi_clk>,

		 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,

		 <&conn_ipg_clk>,

		 <&conn_ipg_clk>;

};



&fec1 {

	compatible = "fsl,imx8qm-fec";

	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;

	assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;

	assigned-clock-rates = <125000000>;

};



&usdhc1 {

	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";

	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

};



&usdhc2 {

	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";

	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;

};



&usdhc3 {

	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";

	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;

};

arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi

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// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright 2020 NXP

 */



&ddr_pmu0 {

	compatible = "fsl,imx8-ddr-pmu";

	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

};

arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi

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// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright 2019~2020, 2022 NXP

 */



&lsio_gpio0 {

	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";

	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;

};



&lsio_gpio1 {

	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";

	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;

};



&lsio_gpio2 {

	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";

	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;

};



&lsio_gpio3 {

	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";

	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;

};



&lsio_gpio4 {

	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";

	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;

};



&lsio_gpio5 {

	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";

	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

};



&lsio_gpio6 {

	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";

	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;

};



&lsio_gpio7 {

	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";

	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

};



&lsio_mu0 {

	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";

	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

};



&lsio_mu1 {

	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";

	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;

};



&lsio_mu2 {

	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";

	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;

};



&lsio_mu3 {

	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";

	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

};



&lsio_mu4 {

	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";

	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;

};



&lsio_mu5 {

	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";

	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;

};

arch/arm64/boot/dts/freescale/imx8dxl.dtsi

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// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright 2019~2020, 2022 NXP

 */



#include <dt-bindings/clock/imx8-clock.h>

#include <dt-bindings/firmware/imx/rsrc.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/input/input.h>

#include <dt-bindings/pinctrl/pads-imx8dxl.h>

#include <dt-bindings/thermal/thermal.h>



/ {

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	aliases {

		ethernet0 = &fec1;

		ethernet1 = &eqos;

		gpio0 = &lsio_gpio0;

		gpio1 = &lsio_gpio1;

		gpio2 = &lsio_gpio2;

		gpio3 = &lsio_gpio3;

		gpio4 = &lsio_gpio4;

		gpio5 = &lsio_gpio5;

		gpio6 = &lsio_gpio6;

		gpio7 = &lsio_gpio7;

		mu1 = &lsio_mu1;

	};



	cpus: cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		/* We have 1 clusters with 2 Cortex-A35 cores */

		A35_0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a35";

			reg = <0x0 0x0>;

			enable-method = "psci";

			next-level-cache = <&A35_L2>;

			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;

			#cooling-cells = <2>;

			operating-points-v2 = <&a35_opp_table>;

		};



		A35_1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a35";

			reg = <0x0 0x1>;

			enable-method = "psci";

			next-level-cache = <&A35_L2>;

			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;

			#cooling-cells = <2>;

			operating-points-v2 = <&a35_opp_table>;

		};



		A35_L2: l2-cache0 {

			compatible = "cache";

		};

	};



	a35_opp_table: opp-table {

		compatible = "operating-points-v2";

		opp-shared;



		opp-900000000 {

			opp-hz = /bits/ 64 <900000000>;

			opp-microvolt = <1000000>;

			clock-latency-ns = <150000>;

		};



		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <1100000>;

			clock-latency-ns = <150000>;

			opp-suspend;

		};

	};



	gic: interrupt-controller@51a00000 {

		compatible = "arm,gic-v3";

		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */

		      <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */

		#interrupt-cells = <3>;

		interrupt-controller;

		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		dsp_reserved: dsp@92400000 {

			reg = <0 0x92400000 0 0x2000000>;

			no-map;

		};

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	system-controller {

		compatible = "fsl,imx-scu";

		mbox-names = "tx0",

			     "rx0",

			     "gip3";

		mboxes = <&lsio_mu1 0 0

			  &lsio_mu1 1 0

			  &lsio_mu1 3 3>;



		pd: power-controller {

			compatible = "fsl,scu-pd";

			#power-domain-cells = <1>;

			wakeup-irq = <160 163 235 236 237 228 229 230 231 238

				     239 240 166 169>;

		};



		clk: clock-controller {

			compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";

			#clock-cells = <2>;

			clocks = <&xtal32k &xtal24m>;

			clock-names = "xtal_32KHz", "xtal_24Mhz";

		};



		iomuxc: pinctrl {

			compatible = "fsl,imx8dxl-iomuxc";

		};



		ocotp: ocotp {

			compatible = "fsl,imx8qxp-scu-ocotp";

			#address-cells = <1>;

			#size-cells = <1>;



			fec_mac0: mac@2c4 {

				reg = <0x2c4 6>;

			};



			fec_mac1: mac@2c6 {

				reg = <0x2c6 6>;

			};

		};



		rtc: rtc {

			compatible = "fsl,imx8qxp-sc-rtc";

		};



		sc_pwrkey: keys {

			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";

			linux,keycode = <KEY_POWER>;

			wakeup-source;

		};



		watchdog {

			compatible = "fsl,imx-sc-wdt";

			timeout-sec = <60>;

		};



		tsens: thermal-sensor {

			compatible = "fsl,imx-sc-thermal";

			#thermal-sensor-cells = <1>;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */

			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */

			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */

			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */

	};



	thermal_zones: thermal-zones {

		cpu-thermal0 {

			polling-delay-passive = <250>;

			polling-delay = <2000>;

			thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;



			trips {

				cpu_alert0: trip0 {

					temperature = <107000>;

					hysteresis = <2000>;

					type = "passive";

				};

				cpu_crit0: trip1 {

					temperature = <127000>;

					hysteresis = <2000>;

					type = "critical";

				};

			};



			cooling-maps {

				map0 {

					trip = <&cpu_alert0>;

					cooling-device =

					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

				};

			};

		};

	};



	/* The two values below cannot be changed by the board */

	xtal32k: clock-xtal32k {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <32768>;

		clock-output-names = "xtal_32KHz";

	};



	xtal24m: clock-xtal24m {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <24000000>;

		clock-output-names = "xtal_24MHz";

	};



	/* sorted in register address */

	#include "imx8-ss-adma.dtsi"

	#include "imx8-ss-conn.dtsi"

	#include "imx8-ss-ddr.dtsi"

	#include "imx8-ss-lsio.dtsi"

};



#include "imx8dxl-ss-adma.dtsi"

#include "imx8dxl-ss-conn.dtsi"

#include "imx8dxl-ss-lsio.dtsi"

#include "imx8dxl-ss-ddr.dtsi"