Commit f531d25b authored by Hector Martin's avatar Hector Martin
Browse files

dt-bindings: interrupt-controller: Add DT bindings for apple-aic 



AIC is the Apple Interrupt Controller found on Apple ARM SoCs, such as
the M1.

Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarHector Martin <marcan@marcan.st>
parent 8a657f71

Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Apple Interrupt Controller



maintainers:

  - Hector Martin <marcan@marcan.st>



description: |

  The Apple Interrupt Controller is a simple interrupt controller present on

  Apple ARM SoC platforms, including various iPhone and iPad devices and the

  "Apple Silicon" Macs.



  It provides the following features:



  - Level-triggered hardware IRQs wired to SoC blocks

    - Single mask bit per IRQ

    - Per-IRQ affinity setting

    - Automatic masking on event delivery (auto-ack)

    - Software triggering (ORed with hw line)

  - 2 per-CPU IPIs (meant as "self" and "other", but they are interchangeable

    if not symmetric)

  - Automatic prioritization (single event/ack register per CPU, lower IRQs =

    higher priority)

  - Automatic masking on ack

  - Default "this CPU" register view and explicit per-CPU views



  This device also represents the FIQ interrupt sources on platforms using AIC,

  which do not go through a discrete interrupt controller.



allOf:

  - $ref: /schemas/interrupt-controller.yaml#



properties:

  compatible:

    items:

      - const: apple,t8103-aic

      - const: apple,aic



  interrupt-controller: true



  '#interrupt-cells':

    const: 3

    description: |

      The 1st cell contains the interrupt type:

        - 0: Hardware IRQ

        - 1: FIQ



      The 2nd cell contains the interrupt number.

        - HW IRQs: interrupt number

        - FIQs:

          - 0: physical HV timer

          - 1: virtual HV timer

          - 2: physical guest timer

          - 3: virtual guest timer



      The 3rd cell contains the interrupt flags. This is normally

      IRQ_TYPE_LEVEL_HIGH (4).



  reg:

    description: |

      Specifies base physical address and size of the AIC registers.

    maxItems: 1



required:

  - compatible

  - '#interrupt-cells'

  - interrupt-controller

  - reg



additionalProperties: false



examples:

  - |

    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        aic: interrupt-controller@23b100000 {

            compatible = "apple,t8103-aic", "apple,aic";

            #interrupt-cells = <3>;

            interrupt-controller;

            reg = <0x2 0x3b100000 0x0 0x8000>;

        };

    };

MAINTAINERS

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@@ -1646,6 +1646,7 @@ B: https://github.com/AsahiLinux/linux/issues 
C:	irc://chat.freenode.net/asahi-dev

T:	git https://github.com/AsahiLinux/linux.git

F:	Documentation/devicetree/bindings/arm/apple.yaml

F:	Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml









ARM/ARTPEC MACHINE SUPPORT









M:	Jesper Nilsson <jesper.nilsson@axis.com>
































include/dt-bindings/interrupt-controller/apple-aic.h
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/* SPDX-License-Identifier: GPL-2.0+ OR MIT */









#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H









#define _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H



















#include <dt-bindings/interrupt-controller/irq.h>



















#define AIC_IRQ	0









#define AIC_FIQ	1



















#define AIC_TMR_HV_PHYS		0









#define AIC_TMR_HV_VIRT		1









#define AIC_TMR_GUEST_PHYS	2









#define AIC_TMR_GUEST_VIRT	3



















#endif