Commit f4ea385a authored by Robert Hancock's avatar Robert Hancock Committed by David S. Miller
Browse files

dt-bindings: net: cdns,macb: added generic PHY and reset mappings for ZynqMP 



Updated macb DT binding documentation to reflect the phy-names, phys,
resets, reset-names properties which are now used with ZynqMP GEM
devices, and added a ZynqMP-specific DT example.

Signed-off-by: default avatarRobert Hancock <robert.hancock@calian.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 0a781172

Documentation/devicetree/bindings/net/cdns,macb.yaml

+56 −0
Original line number Diff line number Diff line
@@ -81,6 +81,25 @@ properties: 


  phy-handle: true



  phys:

    maxItems: 1



  phy-names:

    const: sgmii-phy

    description:

      Required with ZynqMP SoC when in SGMII mode.

      Should reference PS-GTR generic PHY device for this controller

      instance. See ZynqMP example.



  resets:

    maxItems: 1

    description:

      Recommended with ZynqMP, specify reset control for this

      controller instance with zynqmp-reset driver.



  reset-names:

    maxItems: 1



  fixed-link: true



  iommus:
@@ -157,3 +176,40 @@ examples: 
                    reset-gpios = <&pioE 6 1>;

            };

    };



  - |

    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>

    #include <dt-bindings/power/xlnx-zynqmp-power.h>

    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>

    #include <dt-bindings/phy/phy.h>



    bus {

            #address-cells = <2>;

            #size-cells = <2>;

            gem1: ethernet@ff0c0000 {

                    compatible = "cdns,zynqmp-gem", "cdns,gem";

                    interrupt-parent = <&gic>;

                    interrupts = <0 59 4>, <0 59 4>;

                    reg = <0x0 0xff0c0000 0x0 0x1000>;

                    clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,

                             <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,

                             <&zynqmp_clk GEM_TSU>;

                    clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";

                    #address-cells = <1>;

                    #size-cells = <0>;

                    #stream-id-cells = <1>;

                    iommus = <&smmu 0x875>;

                    power-domains = <&zynqmp_firmware PD_ETH_1>;

                    resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;

                    reset-names = "gem1_rst";

                    status = "okay";

                    phy-mode = "sgmii";

                    phy-names = "sgmii-phy";

                    phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>;

                    fixed-link {

                            speed = <1000>;

                            full-duplex;

                            pause;

                    };

            };

    };