Commit f49b6aeb authored Nov 26, 2020 by Loic Poulain Committed by Manivannan Sadhasivam Jan 21, 2021

bus: mhi: Ensure correct ring update ordering with memory barrier

The ring element data, though being part of coherent memory, still need
to be performed before updating the ring context to point to this new
element. That can be guaranteed with a memory barrier (dma_wmb).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

parent ec751369

drivers/bus/mhi/core/main.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -111,7 +111,14 @@ void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl,
		dma_addr_t db;

		db = ring->iommu_base + (ring->wp - ring->base);

		/*
		* Writes to the new ring element must be visible to the hardware
		* before letting h/w know there is new element to fetch.
		*/
		dma_wmb();
		*ring->ctxt_wp = db;

		mhi_chan->db_cfg.process_db(mhi_cntrl, &mhi_chan->db_cfg,
		ring->db_addr, db);
		}