Commit f468ecf1 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Bjorn Andersson
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arm64: dts: qcom: sdm630: Add disabled Venus support



Add support for the Venus video decoder/encoder but leave it disabled
by default; it is expected to eventually get enabled in each machine
specific DT, where required.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211008102119.268869-3-angelogioacchino.delregno@collabora.com
parent 90ba636e
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+51 −0
Original line number Diff line number Diff line
@@ -2014,6 +2014,57 @@
			};
		};

		venus: video-codec@cc00000 {
			compatible = "qcom,sdm660-venus";
			reg = <0x0cc00000 0xff000>;
			clocks = <&mmcc VIDEO_CORE_CLK>,
				 <&mmcc VIDEO_AHB_CLK>,
				 <&mmcc VIDEO_AXI_CLK>,
				 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
			clock-names = "core", "iface", "bus", "bus_throttle";
			interconnects = <&gnoc 0 &mnoc 13>,
					<&mnoc 4 &bimc 5>;
			interconnect-names = "cpu-cfg", "video-mem";
			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
			iommus = <&mmss_smmu 0x400>,
				 <&mmss_smmu 0x401>,
				 <&mmss_smmu 0x40a>,
				 <&mmss_smmu 0x407>,
				 <&mmss_smmu 0x40e>,
				 <&mmss_smmu 0x40f>,
				 <&mmss_smmu 0x408>,
				 <&mmss_smmu 0x409>,
				 <&mmss_smmu 0x40b>,
				 <&mmss_smmu 0x40c>,
				 <&mmss_smmu 0x40d>,
				 <&mmss_smmu 0x410>,
				 <&mmss_smmu 0x421>,
				 <&mmss_smmu 0x428>,
				 <&mmss_smmu 0x429>,
				 <&mmss_smmu 0x42b>,
				 <&mmss_smmu 0x42c>,
				 <&mmss_smmu 0x42d>,
				 <&mmss_smmu 0x411>,
				 <&mmss_smmu 0x431>;
			memory-region = <&venus_region>;
			power-domains = <&mmcc VENUS_GDSC>;
			status = "disabled";

			video-decoder {
				compatible = "venus-decoder";
				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
				clock-names = "vcodec0_core";
				power-domains = <&mmcc VENUS_CORE0_GDSC>;
			};

			video-encoder {
				compatible = "venus-encoder";
				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
				clock-names = "vcodec0_core";
				power-domains = <&mmcc VENUS_CORE0_GDSC>;
			};
		};

		mmss_smmu: iommu@cd00000 {
			compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
			reg = <0x0cd00000 0x40000>;