Commit f455fb65 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/errata' into for-next/core 

* for-next/errata:
  arm64: errata: Workaround possible Cortex-A715 [ESR|FAR]_ELx corruption
  arm64: Add Cortex-715 CPU part definition
parents f6ffa4c8 44ecda71

Documentation/arm64/silicon-errata.rst

+2 −0
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@@ -120,6 +120,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A715     | #2645198        | ARM64_ERRATUM_2645198       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2224489        | ARM64_ERRATUM_2224489       |

arch/arm64/Kconfig

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@@ -968,6 +968,22 @@ config ARM64_ERRATUM_2457168 


	  If unsure, say Y.



config ARM64_ERRATUM_2645198

	bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"

	default y

	help

	  This option adds the workaround for ARM Cortex-A715 erratum 2645198.



	  If a Cortex-A715 cpu sees a page mapping permissions change from executable

	  to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the

	  next instruction abort caused by permission fault.



	  Only user-space does executable to non-executable permission transition via

	  mprotect() system call. Workaround the problem by doing a break-before-make

	  TLB invalidation, for all changes to executable user space mappings.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/cputype.h

+2 −0
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@@ -80,6 +80,7 @@ 
#define ARM_CPU_PART_CORTEX_X1		0xD44

#define ARM_CPU_PART_CORTEX_A510	0xD46

#define ARM_CPU_PART_CORTEX_A710	0xD47

#define ARM_CPU_PART_CORTEX_A715	0xD4D

#define ARM_CPU_PART_CORTEX_X2		0xD48

#define ARM_CPU_PART_NEOVERSE_N2	0xD49

#define ARM_CPU_PART_CORTEX_A78C	0xD4B
@@ -142,6 +143,7 @@ 
#define MIDR_CORTEX_X1	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)

#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)

#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)

#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)

#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)

#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)

#define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)

arch/arm64/include/asm/hugetlb.h

+9 −0
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@@ -49,6 +49,15 @@ extern pte_t huge_ptep_get(pte_t *ptep); 


void __init arm64_hugetlb_cma_reserve(void);



#define huge_ptep_modify_prot_start huge_ptep_modify_prot_start

extern pte_t huge_ptep_modify_prot_start(struct vm_area_struct *vma,

					 unsigned long addr, pte_t *ptep);



#define huge_ptep_modify_prot_commit huge_ptep_modify_prot_commit

extern void huge_ptep_modify_prot_commit(struct vm_area_struct *vma,

					 unsigned long addr, pte_t *ptep,

					 pte_t old_pte, pte_t new_pte);



#include <asm-generic/hugetlb.h>



#endif /* __ASM_HUGETLB_H */

arch/arm64/include/asm/pgtable.h

+9 −0
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@@ -1096,6 +1096,15 @@ static inline bool pud_sect_supported(void) 
}





#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION

#define ptep_modify_prot_start ptep_modify_prot_start

extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma,

				    unsigned long addr, pte_t *ptep);



#define ptep_modify_prot_commit ptep_modify_prot_commit

extern void ptep_modify_prot_commit(struct vm_area_struct *vma,

				    unsigned long addr, pte_t *ptep,

				    pte_t old_pte, pte_t new_pte);

#endif /* !__ASSEMBLY__ */



#endif /* __ASM_PGTABLE_H */