Commit f4499741 authored by Bartlomiej Zolnierkiewicz's avatar Bartlomiej Zolnierkiewicz Committed by Kukjin Kim
Browse files

ARM: dts: add CPU OPP and regulator supply property for exynos4x12 



For Exynos4x12 platforms, add CPU operating points (using
opp-v2 bindings) and CPU regulator supply properties for
migrating from Exynos specific cpufreq driver to using
generic cpufreq driver.

Based on the earlier work by Thomas Abraham.

Cc: Doug Anderson <dianders@chromium.org>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: default avatarJavier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Tested-by: default avatarTobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Tested-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene@kernel.org>
parent 48816aff

arch/arm/boot/dts/exynos4212.dtsi

+81 −0
Original line number Diff line number Diff line
@@ -30,6 +30,9 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0xA00>;

			clocks = <&clock CLK_ARM_CLK>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu0_opp_table>;

			cooling-min-level = <13>;

			cooling-max-level = <7>;

			#cooling-cells = <2>; /* min followed by max */
@@ -39,6 +42,84 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0xA01>;

			operating-points-v2 = <&cpu0_opp_table>;

		};

	};



	cpu0_opp_table: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp00 {

			opp-hz = /bits/ 64 <200000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <200000>;

		};

		opp01 {

			opp-hz = /bits/ 64 <300000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <200000>;

		};

		opp02 {

			opp-hz = /bits/ 64 <400000000>;

			opp-microvolt = <925000>;

			clock-latency-ns = <200000>;

		};

		opp03 {

			opp-hz = /bits/ 64 <500000000>;

			opp-microvolt = <950000>;

			clock-latency-ns = <200000>;

		};

		opp04 {

			opp-hz = /bits/ 64 <600000000>;

			opp-microvolt = <975000>;

			clock-latency-ns = <200000>;

		};

		opp05 {

			opp-hz = /bits/ 64 <700000000>;

			opp-microvolt = <987500>;

			clock-latency-ns = <200000>;

		};

		opp06 {

			opp-hz = /bits/ 64 <800000000>;

			opp-microvolt = <1000000>;

			clock-latency-ns = <200000>;

		};

		opp07 {

			opp-hz = /bits/ 64 <900000000>;

			opp-microvolt = <1037500>;

			clock-latency-ns = <200000>;

		};

		opp08 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <1087500>;

			clock-latency-ns = <200000>;

		};

		opp09 {

			opp-hz = /bits/ 64 <1100000000>;

			opp-microvolt = <1137500>;

			clock-latency-ns = <200000>;

		};

		opp10 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <1187500>;

			clock-latency-ns = <200000>;

		};

		opp11 {

			opp-hz = /bits/ 64 <1300000000>;

			opp-microvolt = <1250000>;

			clock-latency-ns = <200000>;

		};

		opp12 {

			opp-hz = /bits/ 64 <1400000000>;

			opp-microvolt = <1287500>;

			clock-latency-ns = <200000>;

		};

		opp13 {

			opp-hz = /bits/ 64 <1500000000>;

			opp-microvolt = <1350000>;

			clock-latency-ns = <200000>;

			turbo-mode;

		};

	};

};

arch/arm/boot/dts/exynos4412-odroid-common.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -107,6 +107,10 @@ 
	};

};



&cpu0 {

	cpu0-supply = <&buck2_reg>;

};



/* RSTN signal for eMMC */

&sd1_cd {

	samsung,pin-pud = <0>;

arch/arm/boot/dts/exynos4412-origen.dts

+4 −0
Original line number Diff line number Diff line
@@ -78,6 +78,10 @@ 
	};

};



&cpu0 {

	cpu0-supply = <&buck2_reg>;

};



&fimd {

	pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;

	pinctrl-names = "default";

arch/arm/boot/dts/exynos4412-trats2.dts

+4 −0
Original line number Diff line number Diff line
@@ -288,6 +288,10 @@ 
	status = "okay";

};



&cpu0 {

	cpu0-supply = <&buck2_reg>;

};



&csis_0 {

	status = "okay";

	vddcore-supply = <&ldo8_reg>;

arch/arm/boot/dts/exynos4412.dtsi

+83 −0
Original line number Diff line number Diff line
@@ -30,6 +30,9 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0xA00>;

			clocks = <&clock CLK_ARM_CLK>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu0_opp_table>;

			cooling-min-level = <13>;

			cooling-max-level = <7>;

			#cooling-cells = <2>; /* min followed by max */
@@ -39,18 +42,98 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0xA01>;

			operating-points-v2 = <&cpu0_opp_table>;

		};



		cpu@A02 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0xA02>;

			operating-points-v2 = <&cpu0_opp_table>;

		};



		cpu@A03 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0xA03>;

			operating-points-v2 = <&cpu0_opp_table>;

		};

	};



	cpu0_opp_table: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp00 {

			opp-hz = /bits/ 64 <200000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <200000>;

		};

		opp01 {

			opp-hz = /bits/ 64 <300000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <200000>;

		};

		opp02 {

			opp-hz = /bits/ 64 <400000000>;

			opp-microvolt = <925000>;

			clock-latency-ns = <200000>;

		};

		opp03 {

			opp-hz = /bits/ 64 <500000000>;

			opp-microvolt = <950000>;

			clock-latency-ns = <200000>;

		};

		opp04 {

			opp-hz = /bits/ 64 <600000000>;

			opp-microvolt = <975000>;

			clock-latency-ns = <200000>;

		};

		opp05 {

			opp-hz = /bits/ 64 <700000000>;

			opp-microvolt = <987500>;

			clock-latency-ns = <200000>;

		};

		opp06 {

			opp-hz = /bits/ 64 <800000000>;

			opp-microvolt = <1000000>;

			clock-latency-ns = <200000>;

		};

		opp07 {

			opp-hz = /bits/ 64 <900000000>;

			opp-microvolt = <1037500>;

			clock-latency-ns = <200000>;

		};

		opp08 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <1087500>;

			clock-latency-ns = <200000>;

		};

		opp09 {

			opp-hz = /bits/ 64 <1100000000>;

			opp-microvolt = <1137500>;

			clock-latency-ns = <200000>;

		};

		opp10 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <1187500>;

			clock-latency-ns = <200000>;

		};

		opp11 {

			opp-hz = /bits/ 64 <1300000000>;

			opp-microvolt = <1250000>;

			clock-latency-ns = <200000>;

		};

		opp12 {

			opp-hz = /bits/ 64 <1400000000>;

			opp-microvolt = <1287500>;

			clock-latency-ns = <200000>;

		};

		opp13 {

			opp-hz = /bits/ 64 <1500000000>;

			opp-microvolt = <1350000>;

			clock-latency-ns = <200000>;

			turbo-mode;

		};

	};