Commit f42b9e9a authored by Garmin.Chang's avatar Garmin.Chang Committed by Stephen Boyd
Browse files

clk: mediatek: Add MT8188 wpesys clock support 



Add MT8188 wpesys clock controllers which provide clock gate
control in Wrapping Engine.

Signed-off-by: default avatarGarmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230331123621.16167-18-Garmin.Chang@mediatek.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 4898e77f

drivers/clk/mediatek/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -748,6 +748,13 @@ config COMMON_CLK_MT8188_VPPSYS 
	help

	  This driver supports MediaTek MT8188 vppsys0/1 clocks.



config COMMON_CLK_MT8188_WPESYS

	tristate "Clock driver for MediaTek MT8188 wpesys"

	depends on COMMON_CLK_MT8188_IMGSYS

	default COMMON_CLK_MT8188_IMGSYS

	help

	  This driver supports MediaTek MT8188 Warp Engine clocks.



config COMMON_CLK_MT8192

	tristate "Clock driver for MediaTek MT8192"

	depends on ARM64 || COMPILE_TEST

drivers/clk/mediatek/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -110,6 +110,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VDECSYS) += clk-mt8188-vdec.o 
obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) += clk-mt8188-vdo0.o clk-mt8188-vdo1.o

obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) += clk-mt8188-venc.o

obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) += clk-mt8188-vpp0.o clk-mt8188-vpp1.o

obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) += clk-mt8188-wpe.o

obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o

obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o

obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o

drivers/clk/mediatek/clk-mt8188-wpe.c

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+103 −0
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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022 MediaTek Inc.

 * Author: Garmin Chang <garmin.chang@mediatek.com>

 */



#include <dt-bindings/clock/mediatek,mt8188-clk.h>

#include <linux/clk-provider.h>

#include <linux/platform_device.h>



#include "clk-gate.h"

#include "clk-mtk.h"



static const struct mtk_gate_regs wpe_top_cg_regs = {

	.set_ofs = 0x0,

	.clr_ofs = 0x0,

	.sta_ofs = 0x0,

};



static const struct mtk_gate_regs wpe_vpp0_0_cg_regs = {

	.set_ofs = 0x58,

	.clr_ofs = 0x58,

	.sta_ofs = 0x58,

};



static const struct mtk_gate_regs wpe_vpp0_1_cg_regs = {

	.set_ofs = 0x5c,

	.clr_ofs = 0x5c,

	.sta_ofs = 0x5c,

};



#define GATE_WPE_TOP(_id, _name, _parent, _shift)			\

	GATE_MTK(_id, _name, _parent, &wpe_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)



#define GATE_WPE_VPP0_0(_id, _name, _parent, _shift)		\

	GATE_MTK(_id, _name, _parent, &wpe_vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)



#define GATE_WPE_VPP0_1(_id, _name, _parent, _shift)		\

	GATE_MTK(_id, _name, _parent, &wpe_vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)



static const struct mtk_gate wpe_top_clks[] = {

	GATE_WPE_TOP(CLK_WPE_TOP_WPE_VPP0, "wpe_wpe_vpp0", "top_wpe_vpp", 16),

	GATE_WPE_TOP(CLK_WPE_TOP_SMI_LARB7, "wpe_smi_larb7", "top_wpe_vpp", 18),

	GATE_WPE_TOP(CLK_WPE_TOP_WPESYS_EVENT_TX, "wpe_wpesys_event_tx", "top_wpe_vpp", 20),

	GATE_WPE_TOP(CLK_WPE_TOP_SMI_LARB7_PCLK_EN, "wpe_smi_larb7_p_en", "top_wpe_vpp", 24),

};



static const struct mtk_gate wpe_vpp0_clks[] = {

	/* WPE_VPP00 */

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_VGEN, "wpe_vpp0_vgen", "top_img", 0),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_EXT, "wpe_vpp0_ext", "top_img", 1),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_VFC, "wpe_vpp0_vfc", "top_img", 2),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH0_TOP, "wpe_vpp0_cach0_top", "top_img", 3),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH0_DMA, "wpe_vpp0_cach0_dma", "top_img", 4),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH1_TOP, "wpe_vpp0_cach1_top", "top_img", 5),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH1_DMA, "wpe_vpp0_cach1_dma", "top_img", 6),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH2_TOP, "wpe_vpp0_cach2_top", "top_img", 7),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH2_DMA, "wpe_vpp0_cach2_dma", "top_img", 8),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH3_TOP, "wpe_vpp0_cach3_top", "top_img", 9),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH3_DMA, "wpe_vpp0_cach3_dma", "top_img", 10),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_PSP, "wpe_vpp0_psp", "top_img", 11),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_PSP2, "wpe_vpp0_psp2", "top_img", 12),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_SYNC, "wpe_vpp0_sync", "top_img", 13),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_C24, "wpe_vpp0_c24", "top_img", 14),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_MDP_CROP, "wpe_vpp0_mdp_crop", "top_img", 15),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_ISP_CROP, "wpe_vpp0_isp_crop", "top_img", 16),

	GATE_WPE_VPP0_0(CLK_WPE_VPP0_TOP, "wpe_vpp0_top", "top_img", 17),

	/* WPE_VPP0_1 */

	GATE_WPE_VPP0_1(CLK_WPE_VPP0_VECI, "wpe_vpp0_veci", "top_img", 0),

	GATE_WPE_VPP0_1(CLK_WPE_VPP0_VEC2I, "wpe_vpp0_vec2i", "top_img", 1),

	GATE_WPE_VPP0_1(CLK_WPE_VPP0_VEC3I, "wpe_vpp0_vec3i", "top_img", 2),

	GATE_WPE_VPP0_1(CLK_WPE_VPP0_WPEO, "wpe_vpp0_wpeo", "top_img", 3),

	GATE_WPE_VPP0_1(CLK_WPE_VPP0_MSKO, "wpe_vpp0_msko", "top_img", 4),

};



static const struct mtk_clk_desc wpe_top_desc = {

	.clks = wpe_top_clks,

	.num_clks = ARRAY_SIZE(wpe_top_clks),

};



static const struct mtk_clk_desc wpe_vpp0_desc = {

	.clks = wpe_vpp0_clks,

	.num_clks = ARRAY_SIZE(wpe_vpp0_clks),

};



static const struct of_device_id of_match_clk_mt8188_wpe[] = {

	{ .compatible = "mediatek,mt8188-wpesys", .data = &wpe_top_desc },

	{ .compatible = "mediatek,mt8188-wpesys-vpp0", .data = &wpe_vpp0_desc },

	{ /* sentinel */ }

};

MODULE_DEVICE_TABLE(platform, clk_mt8188_vpp1_id_table);



static struct platform_driver clk_mt8188_wpe_drv = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt8188-wpe",

		.of_match_table = of_match_clk_mt8188_wpe,

	},

};



module_platform_driver(clk_mt8188_wpe_drv);

MODULE_LICENSE("GPL");