Commit f3fa86f5 authored by Saleemkhan Jamadar's avatar Saleemkhan Jamadar Committed by Alex Deucher
Browse files

drm/amdgpu:update kernel vcn ring test 



add session context buffer to decoder ring test.

v5 - clear the session ct buffer (Christian)
v4 - data type, explain change of ib size change (Christian)
v3 - indent and  v2 changes correction. (Christian)
v2 - put the buffer at the end of the IB (Christian)

Signed-off-by: default avatarSaleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Acked-by: default avatarLeo Liu <leo.liu@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c1e18c44

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

+11 −2
Original line number Diff line number Diff line
@@ -573,13 +573,15 @@ static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand 
	int r, i;



	memset(ib, 0, sizeof(*ib));

	r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,

	/* 34 pages : 128KiB  session context buffer size and 8KiB ib msg */

	r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 34,

			AMDGPU_IB_POOL_DIRECT,

			ib);

	if (r)

		return r;



	msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);

	memset(msg, 0, (AMDGPU_GPU_PAGE_SIZE * 34));

	msg[0] = cpu_to_le32(0x00000028);

	msg[1] = cpu_to_le32(0x00000038);

	msg[2] = cpu_to_le32(0x00000001);
@@ -608,13 +610,15 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han 
	int r, i;



	memset(ib, 0, sizeof(*ib));

	r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,

	/* 34 pages : 128KiB  session context buffer size and 8KiB ib msg */

	r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 34,

			AMDGPU_IB_POOL_DIRECT,

			ib);

	if (r)

		return r;



	msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);

	memset(msg, 0, (AMDGPU_GPU_PAGE_SIZE * 34));

	msg[0] = cpu_to_le32(0x00000028);

	msg[1] = cpu_to_le32(0x00000018);

	msg[2] = cpu_to_le32(0x00000000);
@@ -700,6 +704,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 
	struct amdgpu_job *job;

	struct amdgpu_ib *ib;

	uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);

	uint64_t session_ctx_buf_gaddr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr + 8192);

	bool sq = amdgpu_vcn_using_unified_queue(ring);

	uint32_t *ib_checksum;

	uint32_t ib_pack_in_dw;
@@ -730,6 +735,10 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, 
	ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;

	memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));



	decode_buffer->valid_buf_flag |=

				cpu_to_le32(AMDGPU_VCN_CMD_FLAG_SESSION_CONTEXT_BUFFER);

	decode_buffer->session_context_buffer_address_hi = upper_32_bits(session_ctx_buf_gaddr);

	decode_buffer->session_context_buffer_address_lo = lower_32_bits(session_ctx_buf_gaddr);

	decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);

	decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);

	decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+4 −1
Original line number Diff line number Diff line
@@ -171,6 +171,7 @@ 


#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER	0x00000001

#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER		0x00000001

#define AMDGPU_VCN_CMD_FLAG_SESSION_CONTEXT_BUFFER	0x00100000



#define VCN_CODEC_DISABLE_MASK_AV1  (1 << 0)

#define VCN_CODEC_DISABLE_MASK_VP9  (1 << 1)
@@ -366,7 +367,9 @@ struct amdgpu_vcn_decode_buffer { 
	uint32_t valid_buf_flag;

	uint32_t msg_buffer_address_hi;

	uint32_t msg_buffer_address_lo;

	uint32_t pad[30];

	uint32_t session_context_buffer_address_hi;

	uint32_t session_context_buffer_address_lo;

	uint32_t pad[28];

};



#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80