Unverified Commit f3bf6add authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!14079 v3 irqchip: gic: some bugfix of hip10 

Merge Pull Request from: @ci-robot 
 
PR sync from: Zhou Wang <wangzhou1@hisilicon.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/Y3ED3WHEKMCKQL3X6JK6MLV65KMQEUAN/ 
Patch#1: add erratum 162200803 for hip10c and exclude GICv4.1 for hip10/hip10c
erratum 162200803.
Patch#2: replace 'is_pending' with 'val' and change hisi cpu type hip09 to hip10.
Patch#3: fix the bug that a large-specification VM fails to be created.

Kunkun Jiang (2):
  KVM: arm64: vgic-v3: Fix a issue of hip10 erratum 162200806
  irqchip/gic-v4.1:Check whether indirect table is supported in
    allocate_vpe_l1_table

Zhou Wang (1):
  irqchip/gic-v3: Exclude GICv4.1 for hip10 erratum 162200803


-- 
2.33.0
 
https://gitee.com/openeuler/kernel/issues/I9KBKD
https://gitee.com/openeuler/kernel/issues/I9SGLA 
 
Link:https://gitee.com/openeuler/kernel/pulls/14079

 

Reviewed-by: default avatarZenghui Yu <yuzenghui@huawei.com>
Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents 01f9633b 69227df0

Documentation/arch/arm64/silicon-errata.rst

+2 −2
Original line number Diff line number Diff line
@@ -256,9 +256,9 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | SMMUv3          | #162100602      | HISILICON_ERRATUM_162100602 |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | Hip09           | #162200803      | N/A                         |

| Hisilicon      | Hip{10,10C}     | #162200803      | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | Hip09           | #162200806      | N/A                         |

| Hisilicon      | Hip10           | #162200806      | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/kvm/vgic/vgic-mmio-v3.c

+1 −1
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu, 
			value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;

			value |= GICD_TYPER_LPIS;

			/* Limit the number of vlpis to 4096 */

			if (kvm_vgic_global_state.flags & FLAGS_WORKAROUND_HIP09_ERRATUM_162200803)

			if (kvm_vgic_global_state.flags & FLAGS_WORKAROUND_HIP10_ERRATUM_162200803)

				value |= 11 << GICD_TYPER_NUM_LPIS_SHIFT;



		} else {

arch/arm64/kvm/vgic/vgic-mmio.c

+7 −8
Original line number Diff line number Diff line
@@ -259,24 +259,23 @@ static unsigned long __read_pending(struct kvm_vcpu *vcpu, 


			if (irq->hw && vgic_irq_is_sgi(irq->intid) &&

			    (kvm_vgic_global_state.flags &

			     FLAGS_WORKAROUND_HIP09_ERRATUM_162200806)) {

			     FLAGS_WORKAROUND_HIP10_ERRATUM_162200806)) {

				void *va;

				u8 *ptr;

				int mask;

				bool is_pending;



				mask = BIT(irq->intid % BITS_PER_BYTE);

				va = page_address(vpe->vpt_page);

				ptr = va + VIRTUAL_SGI_PENDING_OFFSET +

				      irq->intid / BITS_PER_BYTE;

				is_pending = *ptr & mask;

			}



				val = *ptr & mask;

			} else {

				val = false;

				err = irq_get_irqchip_state(irq->host_irq,

						    IRQCHIP_STATE_PENDING,

						    &val);

				WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);

			}

		} else if (!is_user && vgic_irq_is_mapped_level(irq)) {

			val = vgic_get_phys_line_level(irq);

		} else {

arch/arm64/kvm/vgic/vgic-mmio.h

+2 −2
Original line number Diff line number Diff line
@@ -5,8 +5,8 @@ 
#ifndef __KVM_ARM_VGIC_MMIO_H__

#define __KVM_ARM_VGIC_MMIO_H__



#define FLAGS_WORKAROUND_HIP09_ERRATUM_162200803    (1ULL << 4)

#define FLAGS_WORKAROUND_HIP09_ERRATUM_162200806    (1ULL << 5)

#define FLAGS_WORKAROUND_HIP10_ERRATUM_162200803    (1ULL << 4)

#define FLAGS_WORKAROUND_HIP10_ERRATUM_162200806    (1ULL << 5)



struct vgic_register_region {

	unsigned int reg_offset;

drivers/irqchip/irq-gic-v3-its.c

+6 −2
Original line number Diff line number Diff line
@@ -3190,6 +3190,7 @@ static int allocate_vpe_l1_table(void) 
	unsigned int psz = SZ_64K;

	unsigned int np, epp, esz;

	struct page *page;

	bool indirect;



	if (!gic_rdists->has_rvpeid)

		return 0;
@@ -3224,10 +3225,12 @@ static int allocate_vpe_l1_table(void) 


	/* First probe the page size */

	val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K);

	val |= GICR_VPROPBASER_4_1_INDIRECT;

	gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);

	val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER);

	gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);

	esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val);

	indirect = !!(val & GICR_VPROPBASER_4_1_INDIRECT);



	switch (gpsz) {

	default:
@@ -3260,7 +3263,7 @@ static int allocate_vpe_l1_table(void) 
	 * If we need more than just a single L1 page, flag the table

	 * as indirect and compute the number of required L1 pages.

	 */

	if (epp < ITS_MAX_VPEID) {

	if (epp < ITS_MAX_VPEID && indirect) {

		int nl2;



		val |= GICR_VPROPBASER_4_1_INDIRECT;
@@ -3271,7 +3274,8 @@ static int allocate_vpe_l1_table(void) 
		/* Number of L1 pages to point to the L2 pages */

		npg = DIV_ROUND_UP(nl2 * SZ_8, psz);

	} else {

		npg = 1;

		npg = DIV_ROUND_UP(ITS_MAX_VPEID, epp);

		npg = clamp_val(npg, 1, (GICR_VPROPBASER_4_1_SIZE + 1));

	}



	val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1);