Commit f3aaa612 authored by Chris Morgan's avatar Chris Morgan Committed by Heiko Stuebner
Browse files

drm/rockchip: dsi: add rk3568 support 



Add the compatible and GRF definitions for the RK3568 soc.

Signed-off-by: default avatarChris Morgan <macromorgan@hotmail.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20220906174823.28561-4-macroalpha82@gmail.com
parent 1c3b502e

drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c

+49 −2
Original line number Diff line number Diff line
@@ -179,6 +179,23 @@ 
#define RK3399_TXRX_SRC_SEL_ISP0	BIT(4)

#define RK3399_TXRX_TURNREQUEST		GENMASK(3, 0)



#define RK3568_GRF_VO_CON2		0x0368

#define RK3568_DSI0_SKEWCALHS		(0x1f << 11)

#define RK3568_DSI0_FORCETXSTOPMODE	(0xf << 4)

#define RK3568_DSI0_TURNDISABLE		BIT(2)

#define RK3568_DSI0_FORCERXMODE		BIT(0)



/*

 * Note these registers do not appear in the datasheet, they are

 * however present in the BSP driver which is where these values

 * come from. Name GRF_VO_CON3 is assumed.

 */

#define RK3568_GRF_VO_CON3		0x36c

#define RK3568_DSI1_SKEWCALHS		(0x1f << 11)

#define RK3568_DSI1_FORCETXSTOPMODE	(0xf << 4)

#define RK3568_DSI1_TURNDISABLE		BIT(2)

#define RK3568_DSI1_FORCERXMODE		BIT(0)



#define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)



enum {
@@ -735,6 +752,7 @@ static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) 
static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi,

					    int mux)

{

	if (dsi->cdata->lcdsel_grf_reg < 0)

		regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,

			mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);

}
@@ -963,6 +981,8 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev, 
		DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");

		goto out_pll_clk;

	}

	rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder,

						  dev->of_node, 0, 0);



	ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder);

	if (ret) {
@@ -1612,6 +1632,30 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { 
	{ /* sentinel */ }

};



static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {

	{

		.reg = 0xfe060000,

		.lcdsel_grf_reg = -1,

		.lanecfg1_grf_reg = RK3568_GRF_VO_CON2,

		.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS |

					  RK3568_DSI0_FORCETXSTOPMODE |

					  RK3568_DSI0_TURNDISABLE |

					  RK3568_DSI0_FORCERXMODE),

		.max_data_lanes = 4,

	},

	{

		.reg = 0xfe070000,

		.lcdsel_grf_reg = -1,

		.lanecfg1_grf_reg = RK3568_GRF_VO_CON3,

		.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS |

					  RK3568_DSI1_FORCETXSTOPMODE |

					  RK3568_DSI1_TURNDISABLE |

					  RK3568_DSI1_FORCERXMODE),

		.max_data_lanes = 4,

	},

	{ /* sentinel */ }

};



static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {

	{

	 .compatible = "rockchip,px30-mipi-dsi",
@@ -1622,6 +1666,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { 
	}, {

	 .compatible = "rockchip,rk3399-mipi-dsi",

	 .data = &rk3399_chip_data,

	}, {

	 .compatible = "rockchip,rk3568-mipi-dsi",

	 .data = &rk3568_chip_data,

	},

	{ /* sentinel */ }

};