Commit f3a73284 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

ARM: remove sirf prima2/atlas platforms 

The SiRF Prima2 and Atlas platform code was contributed by Cambridge
Silicon Radio (CSR) after aquiring the original SiRF company, and
maintained by Barry Song. CSR was subsequently acquired by Qualcomm,
who no longer have an interest in maintaining the SoC platform but
instead have released more recent SoCs for the same market in the
Snapdragon family.

As Barry is no longer working for the company, nobody else there
wants to maintain it, and there are no third-party users, the
best way forward seems to be to completely remove it.

Thanks to Barry for maintaining the platform for the past ten years.

Cc: Barry Song <baohua@kernel.org>
Link: https://lore.kernel.org/lkml/c969392572604b98bcb3be44048c3165@hisilicon.com/


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent a579fcfa

Documentation/devicetree/bindings/arm/sirf.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/sirf.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: CSR SiRFprimaII and SiRFmarco device tree bindings.



maintainers:

  - Binghua Duan <binghua.duan@csr.com>

  - Barry Song <Baohua.Song@csr.com>



properties:

  $nodename:

    const: '/'

  compatible:

    oneOf:

      - items:

          - const: sirf,atlas6-cb

          - const: sirf,atlas6

      - items:

          - const: sirf,atlas7-cb

          - const: sirf,atlas7

      - items:

          - const: sirf,prima2-cb

          - const: sirf,prima2



additionalProperties: true



...

Documentation/devicetree/bindings/reset/sirf,rstc.txt

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CSR SiRFSoC Reset Controller

======================================



Please also refer to reset.txt in this directory for common reset

controller binding usage.



Required properties:

- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc"

- reg: should be register base and length as documented in the

  datasheet

- #reset-cells: 1, see below



example:



rstc: reset-controller@88010000 {

	compatible = "sirf,prima2-rstc";

	reg = <0x88010000 0x1000>;

	#reset-cells = <1>;

};



Specifying reset lines connected to IP modules

==============================================



The reset controller(rstc) manages various reset sources. This module provides

reset signals for most blocks in system. Those device nodes should specify the

reset line on the rstc in their resets property, containing a phandle to the

rstc device node and a RESET_INDEX specifying which module to reset, as described

in reset.txt.



For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers.

For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose

rest_bit is in SW_RST1, its RESET_INDEX is 32~63.



example:



vpp@90020000 {

	compatible = "sirf,prima2-vpp";

	reg = <0x90020000 0x10000>;

	interrupts = <31>;

	clocks = <&clks 35>;

	resets = <&rstc 6>;

};

MAINTAINERS

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Original line number Diff line number Diff line
@@ -1779,19 +1779,6 @@ F: drivers/net/ethernet/cortina/ 
F:	drivers/pinctrl/pinctrl-gemini.c

F:	drivers/rtc/rtc-ftrtc010.c









ARM/CSR SIRFPRIMA2 MACHINE SUPPORT









M:	Barry Song <baohua@kernel.org>









L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)









S:	Maintained









T:	git git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux.git









F:	arch/arm/boot/dts/prima2*









F:	arch/arm/mach-prima2/









F:	drivers/clk/sirf/









F:	drivers/clocksource/timer-atlas7.c









F:	drivers/clocksource/timer-prima2.c









X:	drivers/gnss









N:	[^a-z]sirf

















ARM/CZ.NIC TURRIS MOX SUPPORT









M:	Marek Behun <marek.behun@nic.cz>









S:	Maintained
































arch/arm/Kconfig



+0
−2






























Original line number
Diff line number
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@@ -671,8 +671,6 @@ source "arch/arm/mach-orion5x/Kconfig"

















source "arch/arm/mach-oxnas/Kconfig"



















source "arch/arm/mach-prima2/Kconfig"



















source "arch/arm/mach-pxa/Kconfig"









source "arch/arm/plat-pxa/Kconfig"










































arch/arm/Kconfig.debug



+2
−39






























Original line number
Diff line number
Diff line







@@ -1142,32 +1142,6 @@ choice







		  Say Y here if you want kernel low-level debugging support









		  on Allwinner A31/A23 based platforms on the R_UART.



















	config DEBUG_SIRFPRIMA2_UART1









		bool "Kernel low-level debugging messages via SiRFprimaII UART1"









		depends on ARCH_PRIMA2









		select DEBUG_SIRFSOC_UART









		help









		  Say Y here if you want the debug print routines to direct









		  their output to the uart1 port on SiRFprimaII devices.



















	config DEBUG_SIRFATLAS7_UART0









		bool "Kernel low-level debugging messages via SiRFatlas7 UART0"









		depends on ARCH_ATLAS7









		select DEBUG_SIRFSOC_UART









		help









		  Say Y here if you want the debug print routines to direct









		  their output to the uart0 port on SiRFATLAS7 devices.The uart0









		  is used on SiRFATLAS7 as a extra debug port.sometimes an extra









		  debug port can be very useful.



















	config DEBUG_SIRFATLAS7_UART1









		bool "Kernel low-level debugging messages via SiRFatlas7 UART1"









		depends on ARCH_ATLAS7









		select DEBUG_SIRFSOC_UART









		help









		  Say Y here if you want the debug print routines to direct









		  their output to the uart1 port on SiRFATLAS7 devices.



















	config DEBUG_SPEAR3XX









		bool "Kernel low-level debugging messages via ST SPEAr 3xx/6xx UART"









		depends on ARCH_SPEAR3XX || ARCH_SPEAR6XX








@@ -1538,10 +1512,6 @@ config DEBUG_STM32_UART







	bool









	depends on ARCH_STM32



















config DEBUG_SIRFSOC_UART









	bool









	depends on ARCH_SIRF



















config DEBUG_UART_FLOW_CONTROL









	bool "Enable flow control (CTS) for the debug UART"









	depends on DEBUG_LL








@@ -1596,7 +1566,6 @@ config DEBUG_LL_INCLUDE







	default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4









	default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART || DEBUG_S3C64XX_UART









	default "debug/s5pv210.S" if DEBUG_S5PV210_UART









	default "debug/sirf.S" if DEBUG_SIRFSOC_UART









	default "debug/sti.S" if DEBUG_STI_UART









	default "debug/stm32.S" if DEBUG_STM32_UART









	default "debug/tegra.S" if DEBUG_TEGRA_UART








@@ -1648,8 +1617,6 @@ config DEBUG_UART_PHYS







	default 0x1600d000 if DEBUG_SD5203_UART









	default 0x18000300 if DEBUG_BCM_5301X









	default 0x18000400 if DEBUG_BCM_HR2









	default 0x18010000 if DEBUG_SIRFATLAS7_UART0









	default 0x18020000 if DEBUG_SIRFATLAS7_UART1









	default 0x18023000 if DEBUG_BCM_IPROC_UART3









	default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1









	default 0x20001000 if DEBUG_HIP01_UART








@@ -1695,7 +1662,6 @@ config DEBUG_UART_PHYS







	default 0x80074000 if DEBUG_IMX28_UART









	default 0x808c0000 if DEBUG_EP93XX || ARCH_EP93XX









	default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART









	default 0xb0060000 if DEBUG_SIRFPRIMA2_UART1









	default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX









	default 0xc0013000 if DEBUG_U300_UART









	default 0xc8000000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN








@@ -1754,7 +1720,7 @@ config DEBUG_UART_PHYS







		DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \









		DEBUG_S3C64XX_UART || \









		DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \









		DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \









		DEBUG_DIGICOLOR_UA0 || \









		DEBUG_AT91_UART || DEBUG_STM32_UART



















config DEBUG_UART_VIRT








@@ -1836,10 +1802,7 @@ config DEBUG_UART_VIRT







	default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1









	default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE









	default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE









	default 0xfec10000 if DEBUG_SIRFATLAS7_UART0









	default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0









	default 0xfec20000 if DEBUG_SIRFATLAS7_UART1









	default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1









	default 0xfec90000 if DEBUG_RK32_UART2









	default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1









	default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART








@@ -1863,7 +1826,7 @@ config DEBUG_UART_VIRT







		DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \









		DEBUG_S3C64XX_UART || \









		DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \









		DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \









		DEBUG_DIGICOLOR_UA0 || \









		DEBUG_AT91_UART || DEBUG_STM32_UART



















config DEBUG_UART_8250_SHIFT