Commit f39157b3 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch irq/gic-6.4 into irq/irqchip-next 



* irq/gic-6.4:
  : .
  : Collection of GIC/GICv3 fixes and cleanups
  :
  : - Workaround for the nvidia T241 chip that gets confused
  :   in 3 and 4 socket configurations, leading to the GIC
  :   malfunctionning in some contexts
  :
  : - Drop support for non-firmware driven GIC configurarations
  :   now that the old ARM11MP Cavium board is gone
  :
  : - Workaround for the Rockchip 3588 chip that doesn't
  :   correctly deal with the shareability attributes.
  : .
  irqchip/gic-v3: Add Rockchip 3588001 erratum workaround
  irqchip/gicv3: Workaround for NVIDIA erratum T241-FABRIC-4
  irqchip/gic: Drop support for board files

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents 197b6b60 a8707f55

Documentation/arm64/silicon-errata.rst

+5 −0
Original line number Diff line number Diff line
@@ -172,6 +172,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| NVIDIA         | Carmel Core     | N/A             | NVIDIA_CARMEL_CNP_ERRATUM   |

+----------------+-----------------+-----------------+-----------------------------+

| NVIDIA         | T241 GICv3/4.x  | T241-FABRIC-4   | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585         |

+----------------+-----------------+-----------------+-----------------------------+
@@ -205,6 +207,9 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo4xx Gold    | N/A             | ARM64_ERRATUM_1286807       |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Rockchip       | RK3588          | #3588001        | ROCKCHIP_ERRATUM_3588001    |

+----------------+-----------------+-----------------+-----------------------------+



+----------------+-----------------+-----------------+-----------------------------+

| Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |

arch/arm64/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -1150,6 +1150,16 @@ config NVIDIA_CARMEL_CNP_ERRATUM 


	  If unsure, say Y.



config ROCKCHIP_ERRATUM_3588001

	bool "Rockchip 3588001: GIC600 can not support shareability attributes"

	default y

	help

	  The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.

	  This means, that its sharability feature may not be used, even though it

	  is supported by the IP itself.



	  If unsure, say Y.



config SOCIONEXT_SYNQUACER_PREITS

	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"

	default y

drivers/firmware/smccc/smccc.c

+26 −0
Original line number Diff line number Diff line
@@ -17,9 +17,13 @@ static enum arm_smccc_conduit smccc_conduit = SMCCC_CONDUIT_NONE; 


bool __ro_after_init smccc_trng_available = false;

u64 __ro_after_init smccc_has_sve_hint = false;

s32 __ro_after_init smccc_soc_id_version = SMCCC_RET_NOT_SUPPORTED;

s32 __ro_after_init smccc_soc_id_revision = SMCCC_RET_NOT_SUPPORTED;



void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)

{

	struct arm_smccc_res res;



	smccc_version = version;

	smccc_conduit = conduit;
@@ -27,6 +31,18 @@ void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit) 
	if (IS_ENABLED(CONFIG_ARM64_SVE) &&

	    smccc_version >= ARM_SMCCC_VERSION_1_3)

		smccc_has_sve_hint = true;



	if ((smccc_version >= ARM_SMCCC_VERSION_1_2) &&

	    (smccc_conduit != SMCCC_CONDUIT_NONE)) {

		arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,

				     ARM_SMCCC_ARCH_SOC_ID, &res);

		if ((s32)res.a0 >= 0) {

			arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_SOC_ID, 0, &res);

			smccc_soc_id_version = (s32)res.a0;

			arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_SOC_ID, 1, &res);

			smccc_soc_id_revision = (s32)res.a0;

		}

	}

}



enum arm_smccc_conduit arm_smccc_1_1_get_conduit(void)
@@ -44,6 +60,16 @@ u32 arm_smccc_get_version(void) 
}

EXPORT_SYMBOL_GPL(arm_smccc_get_version);



s32 arm_smccc_get_soc_id_version(void)

{

	return smccc_soc_id_version;

}



s32 arm_smccc_get_soc_id_revision(void)

{

	return smccc_soc_id_revision;

}



static int __init smccc_devices_init(void)

{

	struct platform_device *pdev;

drivers/firmware/smccc/soc_id.c

+5 −23
Original line number Diff line number Diff line
@@ -42,41 +42,23 @@ static int __init smccc_soc_init(void) 
	if (arm_smccc_get_version() < ARM_SMCCC_VERSION_1_2)

		return 0;



	if (arm_smccc_1_1_get_conduit() == SMCCC_CONDUIT_NONE) {

		pr_err("%s: invalid SMCCC conduit\n", __func__);

		return -EOPNOTSUPP;

	}



	arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,

			     ARM_SMCCC_ARCH_SOC_ID, &res);



	if ((int)res.a0 == SMCCC_RET_NOT_SUPPORTED) {

	soc_id_version = arm_smccc_get_soc_id_version();

	if (soc_id_version == SMCCC_RET_NOT_SUPPORTED) {

		pr_info("ARCH_SOC_ID not implemented, skipping ....\n");

		return 0;

	}



	if ((int)res.a0 < 0) {

		pr_info("ARCH_FEATURES(ARCH_SOC_ID) returned error: %lx\n",

			res.a0);

		return -EINVAL;

	}



	arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_SOC_ID, 0, &res);

	if ((int)res.a0 < 0) {

	if (soc_id_version < 0) {

		pr_err("ARCH_SOC_ID(0) returned error: %lx\n", res.a0);

		return -EINVAL;

	}



	soc_id_version = res.a0;



	arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_SOC_ID, 1, &res);

	if ((int)res.a0 < 0) {

	soc_id_rev = arm_smccc_get_soc_id_revision();

	if (soc_id_rev < 0) {

		pr_err("ARCH_SOC_ID(1) returned error: %lx\n", res.a0);

		return -EINVAL;

	}



	soc_id_rev = res.a0;



	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);

	if (!soc_dev_attr)

		return -ENOMEM;

drivers/irqchip/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ config IRQCHIP 


config ARM_GIC

	bool

	depends on OF

	select IRQ_DOMAIN_HIERARCHY

	select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
@@ -35,6 +36,7 @@ config ARM_GIC_V3 
	select IRQ_DOMAIN_HIERARCHY

	select PARTITION_PERCPU

	select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP

	select HAVE_ARM_SMCCC_DISCOVERY



config ARM_GIC_V3_ITS

	bool