Commit f384720e authored by Jonathan Cameron's avatar Jonathan Cameron
Browse files

dt-bindings:iio:adc: aspeed,ast2400 yaml conversion



Simple txt to yaml conversion. Part of a general move to convert
all the IIO bindings over to yaml.

Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarJoel Stanley <joel@jms.id.au>
Cc: Rick Altherr <raltherr@google.com>
Cc: Joel Stanley <joel@jms.id.au>
Cc: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20200909175946.395313-5-jic23@kernel.org
parent 994235f3
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/aspeed,ast2400-adc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ADC that forms part of an ASPEED server management processor.

maintainers:
  - Joel Stanley <joel@jms.id.au>

description:
  This device is a 10-bit converter for 16 voltage channels.  All inputs are
  single ended.

properties:
  compatible:
    enum:
      - aspeed,ast2400-adc
      - aspeed,ast2500-adc

  reg:
    maxItems: 1

  clocks:
    description:
      Input clock used to derive the sample clock. Expected to be the
      SoC's APB clock.

  resets:
    maxItems: 1

  "#io-channel-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - resets
  - "#io-channel-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/aspeed-clock.h>
    adc@1e6e9000 {
        compatible = "aspeed,ast2400-adc";
        reg = <0x1e6e9000 0xb0>;
        clocks = <&syscon ASPEED_CLK_APB>;
        resets = <&syscon ASPEED_RESET_ADC>;
        #io-channel-cells = <1>;
    };
...
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Aspeed ADC

This device is a 10-bit converter for 16 voltage channels.  All inputs are
single ended.

Required properties:
- compatible: Should be "aspeed,ast2400-adc" or "aspeed,ast2500-adc"
- reg: memory window mapping address and length
- clocks: Input clock used to derive the sample clock. Expected to be the
          SoC's APB clock.
- resets: Reset controller phandle
- #io-channel-cells: Must be set to <1> to indicate channels are selected
                     by index.

Example:
	adc@1e6e9000 {
		compatible = "aspeed,ast2400-adc";
		reg = <0x1e6e9000 0xb0>;
		clocks = <&syscon ASPEED_CLK_APB>;
		resets = <&syscon ASPEED_RESET_ADC>;
		#io-channel-cells = <1>;
	};