Commit f38176d6 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/dwc' 

- Add an imx6 .host_deinit() callback so we can clean up things like
  regulators on probe failure or driver unload (Mark Brown)

- Add PCIE_PME_TO_L2_TIMEOUT_US value for controller drivers that need to
  manually synchronize power removal (Frank Li)

- Add generic dwc suspend/resume APIs (dw_pcie_suspend_noirq() and
  dw_pcie_resume_noirq()) to be called by controller driver suspend/resume
  ops, and a controller callback to send PME_Turn_Off (Frank Li)

- Add layerscape suspend/resume support, including manual
  PME_Turn_off/PME_TO_Ack handshake (Hou Zhiqiang, Frank Li)

* pci/controller/dwc:
  PCI: layerscape: Add power management support for ls1028a
  PCI: dwc: Implement generic suspend/resume functionality
  PCI: Add PCIE_PME_TO_L2_TIMEOUT_US L2 ready timeout value
  PCI: dwc: Provide deinit callback for i.MX
parents 4b3f481c 9fda4d09

drivers/pci/controller/dwc/pci-imx6.c

+1 −0
Original line number Diff line number Diff line
@@ -1040,6 +1040,7 @@ static void imx6_pcie_host_exit(struct dw_pcie_rp *pp) 


static const struct dw_pcie_host_ops imx6_pcie_host_ops = {

	.host_init = imx6_pcie_host_init,

	.host_deinit = imx6_pcie_host_exit,

};



static const struct dw_pcie_ops dw_pcie_ops = {

drivers/pci/controller/dwc/pci-layerscape.c

+131 −9
Original line number Diff line number Diff line
@@ -8,9 +8,11 @@ 
 * Author: Minghuan Lian <Minghuan.Lian@freescale.com>

 */



#include <linux/delay.h>

#include <linux/kernel.h>

#include <linux/interrupt.h>

#include <linux/init.h>

#include <linux/iopoll.h>

#include <linux/of_pci.h>

#include <linux/of_platform.h>

#include <linux/of_address.h>
@@ -20,6 +22,7 @@ 
#include <linux/mfd/syscon.h>

#include <linux/regmap.h>



#include "../../pci.h"

#include "pcie-designware.h"



/* PEX Internal Configuration Registers */
@@ -27,12 +30,26 @@ 
#define PCIE_ABSERR		0x8d0 /* Bridge Slave Error Response Register */

#define PCIE_ABSERR_SETTING	0x9401 /* Forward error of non-posted request */



/* PF Message Command Register */

#define LS_PCIE_PF_MCR		0x2c

#define PF_MCR_PTOMR		BIT(0)

#define PF_MCR_EXL2S		BIT(1)



#define PCIE_IATU_NUM		6



struct ls_pcie_drvdata {

	const u32 pf_off;

	bool pm_support;

};



struct ls_pcie {

	struct dw_pcie *pci;

	const struct ls_pcie_drvdata *drvdata;

	void __iomem *pf_base;

	bool big_endian;

};



#define ls_pcie_pf_readl_addr(addr)	ls_pcie_pf_readl(pcie, addr)

#define to_ls_pcie(x)	dev_get_drvdata((x)->dev)



static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
@@ -73,6 +90,68 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie) 
	iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);

}



static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off)

{

	if (pcie->big_endian)

		return ioread32be(pcie->pf_base + off);



	return ioread32(pcie->pf_base + off);

}



static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val)

{

	if (pcie->big_endian)

		iowrite32be(val, pcie->pf_base + off);

	else

		iowrite32(val, pcie->pf_base + off);

}



static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct ls_pcie *pcie = to_ls_pcie(pci);

	u32 val;

	int ret;



	val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);

	val |= PF_MCR_PTOMR;

	ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);



	ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,

				 val, !(val & PF_MCR_PTOMR),

				 PCIE_PME_TO_L2_TIMEOUT_US/10,

				 PCIE_PME_TO_L2_TIMEOUT_US);

	if (ret)

		dev_err(pcie->pci->dev, "PME_Turn_off timeout\n");

}



static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct ls_pcie *pcie = to_ls_pcie(pci);

	u32 val;

	int ret;



	/*

	 * Set PF_MCR_EXL2S bit in LS_PCIE_PF_MCR register for the link

	 * to exit L2 state.

	 */

	val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);

	val |= PF_MCR_EXL2S;

	ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);



	/*

	 * L2 exit timeout of 10ms is not defined in the specifications,

	 * it was chosen based on empirical observations.

	 */

	ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,

				 val, !(val & PF_MCR_EXL2S),

				 1000,

				 10000);

	if (ret)

		dev_err(pcie->pci->dev, "L2 exit timeout\n");

}



static int ls_pcie_host_init(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
@@ -91,18 +170,28 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) 


static const struct dw_pcie_host_ops ls_pcie_host_ops = {

	.host_init = ls_pcie_host_init,

	.pme_turn_off = ls_pcie_send_turnoff_msg,

};



static const struct ls_pcie_drvdata ls1021a_drvdata = {

	.pm_support = false,

};



static const struct ls_pcie_drvdata layerscape_drvdata = {

	.pf_off = 0xc0000,

	.pm_support = true,

};



static const struct of_device_id ls_pcie_of_match[] = {

	{ .compatible = "fsl,ls1012a-pcie", },

	{ .compatible = "fsl,ls1021a-pcie", },

	{ .compatible = "fsl,ls1028a-pcie", },

	{ .compatible = "fsl,ls1043a-pcie", },

	{ .compatible = "fsl,ls1046a-pcie", },

	{ .compatible = "fsl,ls2080a-pcie", },

	{ .compatible = "fsl,ls2085a-pcie", },

	{ .compatible = "fsl,ls2088a-pcie", },

	{ .compatible = "fsl,ls1088a-pcie", },

	{ .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata },

	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata },

	{ .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata },

	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata },

	{ .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata },

	{ .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata },

	{ .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata },

	{ .compatible = "fsl,ls2088a-pcie", .data = &layerscape_drvdata },

	{ .compatible = "fsl,ls1088a-pcie", .data = &layerscape_drvdata },

	{ },

};
@@ -121,6 +210,8 @@ static int ls_pcie_probe(struct platform_device *pdev) 
	if (!pci)

		return -ENOMEM;



	pcie->drvdata = of_device_get_match_data(dev);



	pci->dev = dev;

	pci->pp.ops = &ls_pcie_host_ops;
@@ -131,6 +222,10 @@ static int ls_pcie_probe(struct platform_device *pdev) 
	if (IS_ERR(pci->dbi_base))

		return PTR_ERR(pci->dbi_base);



	pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian");



	pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off;



	if (!ls_pcie_is_bridge(pcie))

		return -ENODEV;
@@ -139,12 +234,39 @@ static int ls_pcie_probe(struct platform_device *pdev) 
	return dw_pcie_host_init(&pci->pp);

}



static int ls_pcie_suspend_noirq(struct device *dev)

{

	struct ls_pcie *pcie = dev_get_drvdata(dev);



	if (!pcie->drvdata->pm_support)

		return 0;



	return dw_pcie_suspend_noirq(pcie->pci);

}



static int ls_pcie_resume_noirq(struct device *dev)

{

	struct ls_pcie *pcie = dev_get_drvdata(dev);



	if (!pcie->drvdata->pm_support)

		return 0;



	ls_pcie_exit_from_l2(&pcie->pci->pp);



	return dw_pcie_resume_noirq(pcie->pci);

}



static const struct dev_pm_ops ls_pcie_pm_ops = {

	NOIRQ_SYSTEM_SLEEP_PM_OPS(ls_pcie_suspend_noirq, ls_pcie_resume_noirq)

};



static struct platform_driver ls_pcie_driver = {

	.probe = ls_pcie_probe,

	.driver = {

		.name = "layerscape-pcie",

		.of_match_table = ls_pcie_of_match,

		.suppress_bind_attrs = true,

		.pm = &ls_pcie_pm_ops,

	},

};

builtin_platform_driver(ls_pcie_driver);

drivers/pci/controller/dwc/pcie-designware-host.c

+71 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
 * Author: Jingoo Han <jg1.han@samsung.com>

 */



#include <linux/iopoll.h>

#include <linux/irqchip/chained_irq.h>

#include <linux/irqdomain.h>

#include <linux/msi.h>
@@ -16,6 +17,7 @@ 
#include <linux/pci_regs.h>

#include <linux/platform_device.h>



#include "../../pci.h"

#include "pcie-designware.h"



static struct pci_ops dw_pcie_ops;
@@ -812,3 +814,72 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) 
	return 0;

}

EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);



int dw_pcie_suspend_noirq(struct dw_pcie *pci)

{

	u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);

	u32 val;

	int ret;



	/*

	 * If L1SS is supported, then do not put the link into L2 as some

	 * devices such as NVMe expect low resume latency.

	 */

	if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1)

		return 0;



	if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT)

		return 0;



	if (!pci->pp.ops->pme_turn_off)

		return 0;



	pci->pp.ops->pme_turn_off(&pci->pp);



	ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,

				PCIE_PME_TO_L2_TIMEOUT_US/10,

				PCIE_PME_TO_L2_TIMEOUT_US, false, pci);

	if (ret) {

		dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val);

		return ret;

	}



	if (pci->pp.ops->host_deinit)

		pci->pp.ops->host_deinit(&pci->pp);



	pci->suspended = true;



	return ret;

}

EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq);



int dw_pcie_resume_noirq(struct dw_pcie *pci)

{

	int ret;



	if (!pci->suspended)

		return 0;



	pci->suspended = false;



	if (pci->pp.ops->host_init) {

		ret = pci->pp.ops->host_init(&pci->pp);

		if (ret) {

			dev_err(pci->dev, "Host init failed: %d\n", ret);

			return ret;

		}

	}



	dw_pcie_setup_rc(&pci->pp);



	ret = dw_pcie_start_link(pci);

	if (ret)

		return ret;



	ret = dw_pcie_wait_for_link(pci);

	if (ret)

		return ret;



	return ret;

}

EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq);

drivers/pci/controller/dwc/pcie-designware.h

+28 −0
Original line number Diff line number Diff line
@@ -288,10 +288,21 @@ enum dw_pcie_core_rst { 
	DW_PCIE_NUM_CORE_RSTS

};



enum dw_pcie_ltssm {

	/* Need to align with PCIE_PORT_DEBUG0 bits 0:5 */

	DW_PCIE_LTSSM_DETECT_QUIET = 0x0,

	DW_PCIE_LTSSM_DETECT_ACT = 0x1,

	DW_PCIE_LTSSM_L0 = 0x11,

	DW_PCIE_LTSSM_L2_IDLE = 0x15,



	DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF,

};



struct dw_pcie_host_ops {

	int (*host_init)(struct dw_pcie_rp *pp);

	void (*host_deinit)(struct dw_pcie_rp *pp);

	int (*msi_host_init)(struct dw_pcie_rp *pp);

	void (*pme_turn_off)(struct dw_pcie_rp *pp);

};



struct dw_pcie_rp {
@@ -364,6 +375,7 @@ struct dw_pcie_ops { 
	void    (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg,

			      size_t size, u32 val);

	int	(*link_up)(struct dw_pcie *pcie);

	enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie);

	int	(*start_link)(struct dw_pcie *pcie);

	void	(*stop_link)(struct dw_pcie *pcie);

};
@@ -393,6 +405,7 @@ struct dw_pcie { 
	struct reset_control_bulk_data	app_rsts[DW_PCIE_NUM_APP_RSTS];

	struct reset_control_bulk_data	core_rsts[DW_PCIE_NUM_CORE_RSTS];

	struct gpio_desc		*pe_rst;

	bool			suspended;

};



#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
@@ -431,6 +444,9 @@ int dw_pcie_edma_detect(struct dw_pcie *pci); 
void dw_pcie_edma_remove(struct dw_pcie *pci);

void dw_pcie_print_link_status(struct dw_pcie *pci);



int dw_pcie_suspend_noirq(struct dw_pcie *pci);

int dw_pcie_resume_noirq(struct dw_pcie *pci);



static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)

{

	dw_pcie_write_dbi(pci, reg, 0x4, val);
@@ -502,6 +518,18 @@ static inline void dw_pcie_stop_link(struct dw_pcie *pci) 
		pci->ops->stop_link(pci);

}



static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)

{

	u32 val;



	if (pci->ops && pci->ops->get_ltssm)

		return pci->ops->get_ltssm(pci);



	val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);



	return (enum dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK, val);

}



#ifdef CONFIG_PCIE_DW_HOST

irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);

int dw_pcie_setup_rc(struct dw_pcie_rp *pp);

drivers/pci/pci.h

+6 −0
Original line number Diff line number Diff line
@@ -13,6 +13,12 @@ 


#define PCIE_LINK_RETRAIN_TIMEOUT_MS	1000



/*

 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>

 * Recommends 1ms to 10ms timeout to check L2 ready.

 */

#define PCIE_PME_TO_L2_TIMEOUT_US	10000



extern const unsigned char pcie_link_speed[];

extern bool pci_early_dump;