Commit f371f8eb authored by Joey Gouly's avatar Joey Gouly Committed by Zheng Zengkai
Browse files

arm64: add ID_AA64ISAR2_EL1 sys register 

stable inclusion
from stable-v5.10.105
commit dbcfa98539531bff0d7e4d6087741702dfa50f06
bugzilla: 186480 https://gitee.com/src-openeuler/kernel/issues/I53MHA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=dbcfa98539531bff0d7e4d6087741702dfa50f06



--------------------------------

commit 9e45365f upstream.

This is a new ID register, introduced in 8.7.

Signed-off-by: default avatarJoey Gouly <joey.gouly@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Reiji Watanabe <reijiw@google.com>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211210165432.8106-3-joey.gouly@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: default avatarChen Jun <chenjun102@huawei.com>
Reviewed-by: default avatarLiao Chang <liaochang1@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 62641ba9

arch/arm64/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ struct cpuinfo_arm64 { 
	u64		reg_id_aa64dfr1;

	u64		reg_id_aa64isar0;

	u64		reg_id_aa64isar1;

	u64		reg_id_aa64isar2;

	u64		reg_id_aa64mmfr0;

	u64		reg_id_aa64mmfr1;

	u64		reg_id_aa64mmfr2;

arch/arm64/include/asm/sysreg.h

+15 −0
Original line number Diff line number Diff line
@@ -179,6 +179,7 @@ 


#define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)

#define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)

#define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)



#define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)

#define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
@@ -705,6 +706,20 @@ 
#define ID_AA64ISAR1_GPI_NI			0x0

#define ID_AA64ISAR1_GPI_IMP_DEF		0x1



/* id_aa64isar2 */

#define ID_AA64ISAR2_RPRES_SHIFT	4

#define ID_AA64ISAR2_WFXT_SHIFT		0



#define ID_AA64ISAR2_RPRES_8BIT		0x0

#define ID_AA64ISAR2_RPRES_12BIT	0x1

/*

 * Value 0x1 has been removed from the architecture, and is

 * reserved, but has not yet been removed from the ARM ARM

 * as of ARM DDI 0487G.b.

 */

#define ID_AA64ISAR2_WFXT_NI		0x0

#define ID_AA64ISAR2_WFXT_SUPPORTED	0x2



/* id_aa64pfr0 */

#define ID_AA64PFR0_CSV3_SHIFT		60

#define ID_AA64PFR0_CSV2_SHIFT		56

arch/arm64/kernel/cpufeature.c

+9 −0
Original line number Diff line number Diff line
@@ -201,6 +201,10 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 
	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {

	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
@@ -592,6 +596,7 @@ static const struct __ftr_reg_entry { 
	/* Op1 = 0, CRn = 0, CRm = 6 */

	ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),

	ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),

	ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),



	/* Op1 = 0, CRn = 0, CRm = 7 */

	ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
@@ -826,6 +831,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) 
	init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);

	init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);

	init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);

	init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);

	init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);

	init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);

	init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
@@ -1054,6 +1060,8 @@ void update_cpu_features(int cpu, 
				      info->reg_id_aa64isar0, boot->reg_id_aa64isar0);

	taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,

				      info->reg_id_aa64isar1, boot->reg_id_aa64isar1);

	taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,

				      info->reg_id_aa64isar2, boot->reg_id_aa64isar2);



	/*

	 * Differing PARange support is fine as long as all peripherals and
@@ -1166,6 +1174,7 @@ static u64 __read_sysreg_by_encoding(u32 sys_id) 
	read_sysreg_case(SYS_ID_AA64MMFR2_EL1);

	read_sysreg_case(SYS_ID_AA64ISAR0_EL1);

	read_sysreg_case(SYS_ID_AA64ISAR1_EL1);

	read_sysreg_case(SYS_ID_AA64ISAR2_EL1);



	read_sysreg_case(SYS_CNTFRQ_EL0);

	read_sysreg_case(SYS_CTR_EL0);

arch/arm64/kernel/cpuinfo.c

+1 −0
Original line number Diff line number Diff line
@@ -365,6 +365,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
	info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);

	info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);

	info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);

	info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);

	info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);

	info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);

	info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);

arch/arm64/kvm/sys_regs.c

+1 −1
Original line number Diff line number Diff line
@@ -1548,7 +1548,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	/* CRm=6 */

	ID_SANITISED(ID_AA64ISAR0_EL1),

	ID_SANITISED(ID_AA64ISAR1_EL1),

	ID_UNALLOCATED(6,2),

	ID_SANITISED(ID_AA64ISAR2_EL1),

	ID_UNALLOCATED(6,3),

	ID_UNALLOCATED(6,4),

	ID_UNALLOCATED(6,5),