Commit f36edc55 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-5.13-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC fixes from Vineet Gupta:

 - PAE fixes

 - syscall num check off-by-one bug

 - misc fixes

* tag 'arc-5.13-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: mm: Use max_high_pfn as a HIGHMEM zone border
  ARC: mm: PAE: use 40-bit physical page mask
  ARC: entry: fix off-by-one error in syscall number validation
  ARC: kgdb: add 'fallthrough' to prevent a warning
  arc: Fix typos/spellos
parents 8f4ae0f6 1d5e4640

arch/arc/Makefile

+1 −1
Original line number Original line Diff line number Diff line
@@ -31,7 +31,7 @@ endif 








ifdef CONFIG_ARC_CURR_IN_REG

ifdef CONFIG_ARC_CURR_IN_REG

# For a global register defintion, make sure it gets passed to every file

# For a global register definition, make sure it gets passed to every file

# We had a customer reported bug where some code built in kernel was NOT using

# We had a customer reported bug where some code built in kernel was NOT using

# any kernel headers, and missing the r25 global register

# any kernel headers, and missing the r25 global register

# Can't do unconditionally because of recursive include issues

# Can't do unconditionally because of recursive include issues

arch/arc/include/asm/cmpxchg.h

+2 −2
Original line number Original line Diff line number Diff line
@@ -116,7 +116,7 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr, 
 *

 *

 * Technically the lock is also needed for UP (boils down to irq save/restore)

 * Technically the lock is also needed for UP (boils down to irq save/restore)

 * but we can cheat a bit since cmpxchg() atomic_ops_lock() would cause irqs to

 * but we can cheat a bit since cmpxchg() atomic_ops_lock() would cause irqs to

 * be disabled thus can't possibly be interrpted/preempted/clobbered by xchg()

 * be disabled thus can't possibly be interrupted/preempted/clobbered by xchg()

 * Other way around, xchg is one instruction anyways, so can't be interrupted

 * Other way around, xchg is one instruction anyways, so can't be interrupted

 * as such

 * as such

 */

 */
@@ -143,7 +143,7 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr, 
/*

/*

 * "atomic" variant of xchg()

 * "atomic" variant of xchg()

 * REQ: It needs to follow the same serialization rules as other atomic_xxx()

 * REQ: It needs to follow the same serialization rules as other atomic_xxx()

 * Since xchg() doesn't always do that, it would seem that following defintion

 * Since xchg() doesn't always do that, it would seem that following definition

 * is incorrect. But here's the rationale:

 * is incorrect. But here's the rationale:

 *   SMP : Even xchg() takes the atomic_ops_lock, so OK.

 *   SMP : Even xchg() takes the atomic_ops_lock, so OK.

 *   LLSC: atomic_ops_lock are not relevant at all (even if SMP, since LLSC

 *   LLSC: atomic_ops_lock are not relevant at all (even if SMP, since LLSC

arch/arc/include/asm/page.h

+12 −0
Original line number Original line Diff line number Diff line
@@ -7,6 +7,18 @@ 




#include <uapi/asm/page.h>

#include <uapi/asm/page.h>





#ifdef CONFIG_ARC_HAS_PAE40



#define MAX_POSSIBLE_PHYSMEM_BITS	40

#define PAGE_MASK_PHYS			(0xff00000000ull | PAGE_MASK)



#else /* CONFIG_ARC_HAS_PAE40 */



#define MAX_POSSIBLE_PHYSMEM_BITS	32

#define PAGE_MASK_PHYS			PAGE_MASK



#endif /* CONFIG_ARC_HAS_PAE40 */



#ifndef __ASSEMBLY__

#ifndef __ASSEMBLY__





#define clear_page(paddr)		memset((paddr), 0, PAGE_SIZE)

#define clear_page(paddr)		memset((paddr), 0, PAGE_SIZE)

arch/arc/include/asm/pgtable.h

+3 −9
Original line number Original line Diff line number Diff line
@@ -107,8 +107,8 @@ 
#define ___DEF (_PAGE_PRESENT | _PAGE_CACHEABLE)

#define ___DEF (_PAGE_PRESENT | _PAGE_CACHEABLE)





/* Set of bits not changed in pte_modify */

/* Set of bits not changed in pte_modify */

#define _PAGE_CHG_MASK	(PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_SPECIAL)

#define _PAGE_CHG_MASK	(PAGE_MASK_PHYS | _PAGE_ACCESSED | _PAGE_DIRTY | \



							   _PAGE_SPECIAL)

/* More Abbrevaited helpers */

/* More Abbrevaited helpers */

#define PAGE_U_NONE     __pgprot(___DEF)

#define PAGE_U_NONE     __pgprot(___DEF)

#define PAGE_U_R        __pgprot(___DEF | _PAGE_READ)

#define PAGE_U_R        __pgprot(___DEF | _PAGE_READ)
@@ -132,13 +132,7 @@ 
#define PTE_BITS_IN_PD0		(_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_HW_SZ)

#define PTE_BITS_IN_PD0		(_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_HW_SZ)

#define PTE_BITS_RWX		(_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ)

#define PTE_BITS_RWX		(_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ)





#ifdef CONFIG_ARC_HAS_PAE40

#define PTE_BITS_NON_RWX_IN_PD1	(PAGE_MASK_PHYS | _PAGE_CACHEABLE)

#define PTE_BITS_NON_RWX_IN_PD1	(0xff00000000 | PAGE_MASK | _PAGE_CACHEABLE)

#define MAX_POSSIBLE_PHYSMEM_BITS 40

#else

#define PTE_BITS_NON_RWX_IN_PD1	(PAGE_MASK | _PAGE_CACHEABLE)

#define MAX_POSSIBLE_PHYSMEM_BITS 32

#endif





/**************************************************************************

/**************************************************************************

 * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)

 * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)

arch/arc/include/uapi/asm/page.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -33,5 +33,4 @@ 




#define PAGE_MASK	(~(PAGE_SIZE-1))

#define PAGE_MASK	(~(PAGE_SIZE-1))







#endif /* _UAPI__ASM_ARC_PAGE_H */
 
#endif /* _UAPI__ASM_ARC_PAGE_H */