Commit f35534a2 authored Oct 01, 2020 by Vineet Gupta

ARC: mm: hack to allow 2 level build with 4 level code



PMD_SHIFT is mapped to PUD_SHIFT or PGD_SHIFT by asm-generic/pgtable-*
but only for !__ASSEMBLY__

tlbex.S asm code has PTRS_PER_PTE which uses PMD_SHIFT hence barfs
for CONFIG_PGTABLE_LEVEL={2,3} and works for 4.

So add a workaround local to tlbex.S - the proper fix is to change
asm-generic/pgtable-* headers to expose the defines for __ASSEMBLY__ too

Signed-off-by: Vineet Gupta <vgupta@kernel.org>

parent fe6cb7b0

arch/arc/mm/tlbex.S

+8 −0

Original line number	Diff line number	Diff line
		@@ -145,6 +145,14 @@ ex_saved_reg1:
		;TLB Miss handling Code
		;============================================================================

		#ifndef PMD_SHIFT
		#define PMD_SHIFT PUD_SHIFT
		#endif

		#ifndef PUD_SHIFT
		#define PUD_SHIFT PGDIR_SHIFT
		#endif

		;-----------------------------------------------------------------------------
		; This macro does the page-table lookup for the faulting address.
		; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address