Unverified Commit f32a2bcb authored by Simon Trimmer's avatar Simon Trimmer Committed by Mark Brown
Browse files

ASoC: cs35l56: Make common function for control port wait 



Move the waits for CS35L56_CONTROL_PORT_READY_US into a common
function, and also allow a wider range of allowed wait times.

Signed-off-by: default avatarSimon Trimmer <simont@opensource.cirrus.com>
Signed-off-by: default avatarRichard Fitzgerald <rf@opensource.cirrus.com>
Acked-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230721132120.5523-9-rf@opensource.cirrus.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 84851aa0

include/sound/cs35l56.h

+1 −0
Original line number Diff line number Diff line
@@ -275,6 +275,7 @@ extern const unsigned int cs35l56_tx_input_values[CS35L56_NUM_INPUT_SRC]; 
int cs35l56_set_patch(struct cs35l56_base *cs35l56_base);

int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command);

int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base);

void cs35l56_wait_control_port_ready(void);

void cs35l56_wait_min_reset_pulse(void);

void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire);

int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq);

sound/soc/codecs/cs35l56-shared.c

+10 −6
Original line number Diff line number Diff line
@@ -244,6 +244,13 @@ int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 
}

EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED);



void cs35l56_wait_control_port_ready(void)

{

	/* Wait for control port to be ready (datasheet tIRS). */

	usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US);

}

EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED);



void cs35l56_wait_min_reset_pulse(void)

{

	/* Satisfy minimum reset pulse width spec */
@@ -270,7 +277,7 @@ void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 
	if (is_soundwire)

		return;



	usleep_range(CS35L56_CONTROL_PORT_READY_US, CS35L56_CONTROL_PORT_READY_US + 400);

	cs35l56_wait_control_port_ready();

	regcache_cache_only(cs35l56_base->regmap, false);

}

EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED);
@@ -481,8 +488,7 @@ int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_sou 
						cs35l56_hibernate_wake_seq,

						ARRAY_SIZE(cs35l56_hibernate_wake_seq));



		usleep_range(CS35L56_CONTROL_PORT_READY_US,

			     CS35L56_CONTROL_PORT_READY_US + 400);

		cs35l56_wait_control_port_ready();

	}



out_sync:
@@ -556,9 +562,7 @@ int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 
	if (!cs35l56_base->reset_gpio)

		regmap_read(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, &devid);



	/* Wait for control port to be ready (datasheet tIRS). */

	usleep_range(CS35L56_CONTROL_PORT_READY_US,

		     CS35L56_CONTROL_PORT_READY_US + 400);

	cs35l56_wait_control_port_ready();



	/*

	 * The HALO_STATE register is in different locations on Ax and B0