Commit f31531e5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2021-10-29' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Quiet but not too quiet, I blame Halloween.

  The first set of amdgpu fixes missed last week, hence why this has a
  few more of them, it's mostly display fixes for new GPUs and some
  debugfs OOB stuff.

  The i915 patches have one to remove a tracepoint possible issue before
  it's a real problem, the others around cflush and display are cc'ed to
  stable as well.

  Otherwise it's just a few misc fixes.

  Summary:

  MAINTAINERS:
   - Fix the path pattern

  ttm:
   - Fix fence leak in ttm_transfered_destroy.

  core:
   - Add GPD Win3 rotation quirk

  i915:
   - Remove unconditional clflushes
   - Fix oops on boot due to sync state on disabled DP encoders
   - Revert backend specific data added to tracepoints
   - Remove useless and incorrect memory frequence calculation

  panel:
   - Add quirk for Aya Neo 2021

  seltest:
   - Reset property count for each drm damage selftest so full run will
     work correctly.

  amdgpu:
   - Fix two potential out of bounds writes in debugfs
   - Fix revision handling for Yellow Carp
   - Display fixes for Yellow Carp
   - Display fixes for DCN 3.1"

* tag 'drm-fixes-2021-10-29' of git://anongit.freedesktop.org/drm/drm: (21 commits)
  MAINTAINERS: dri-devel is for all of drivers/gpu
  drm/i915: Revert 'guc_id' from i915_request tracepoint
  drm/amd/display: Fix deadlock when falling back to v2 from v3
  drm/amd/display: Fallback to clocks which meet requested voltage on DCN31
  drm/amdgpu: Fix even more out of bound writes from debugfs
  drm: panel-orientation-quirks: Add quirk for GPD Win3
  drm/i915/dp: Skip the HW readout of DPCD on disabled encoders
  drm/i915: Catch yet another unconditioal clflush
  drm/i915: Convert unconditional clflush to drm_clflush_virt_range()
  drm/i915/selftests: Properly reset mock object propers for each test
  drm: panel-orientation-quirks: Add quirk for Aya Neo 2021
  drm/ttm: fix memleak in ttm_transfered_destroy
  drm/amdgpu: support B0&B1 external revision id for yellow carp
  drm/amd/display: Moved dccg init to after bios golden init
  drm/amd/display: Increase watermark latencies for DCN3.1
  drm/amd/display: increase Z9 latency to workaround underflow in Z9
  drm/amd/display: Require immediate flip support for DCN3.1 planes
  drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1
  drm/amd/display: Limit display scaling to up to true 4k for DCN 3.1
  drm/amdgpu: fix out of bounds write
  ...
parents 411a44c2 b112166a

MAINTAINERS

+1 −2
Original line number Diff line number Diff line
@@ -6160,8 +6160,7 @@ T: git git://anongit.freedesktop.org/drm/drm 
F:	Documentation/devicetree/bindings/display/

F:	Documentation/devicetree/bindings/gpu/

F:	Documentation/gpu/

F:	drivers/gpu/drm/

F:	drivers/gpu/vga/

F:	drivers/gpu/

F:	include/drm/

F:	include/linux/vga*

F:	include/uapi/drm/

drivers/gpu/drm/amd/amdgpu/nv.c

+1 −1
Original line number Diff line number Diff line
@@ -1257,7 +1257,7 @@ static int nv_common_early_init(void *handle) 
			AMD_PG_SUPPORT_VCN_DPG |

			AMD_PG_SUPPORT_JPEG;

		if (adev->pdev->device == 0x1681)

			adev->external_rev_id = adev->rev_id + 0x19;

			adev->external_rev_id = 0x20;

		else

			adev->external_rev_id = adev->rev_id + 0x01;

		break;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

+10 −10
Original line number Diff line number Diff line
@@ -263,7 +263,7 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 
	if (!wr_buf)

		return -ENOSPC;



	if (parse_write_buffer_into_params(wr_buf, size,

	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,

					   (long *)param, buf,

					   max_param_num,

					   &param_nums)) {
@@ -487,7 +487,7 @@ static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 
	if (!wr_buf)

		return -ENOSPC;



	if (parse_write_buffer_into_params(wr_buf, size,

	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,

					   (long *)param, buf,

					   max_param_num,

					   &param_nums)) {
@@ -639,7 +639,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us 
	if (!wr_buf)

		return -ENOSPC;



	if (parse_write_buffer_into_params(wr_buf, size,

	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,

					   (long *)param, buf,

					   max_param_num,

					   &param_nums)) {
@@ -914,7 +914,7 @@ static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 
		return -ENOSPC;

	}



	if (parse_write_buffer_into_params(wr_buf, size,

	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,

					   &param, buf,

					   max_param_num,

					   &param_nums)) {
@@ -1211,7 +1211,7 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 
		return -ENOSPC;

	}



	if (parse_write_buffer_into_params(wr_buf, size,

	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,

						(long *)param, buf,

						max_param_num,

						&param_nums)) {
@@ -1396,7 +1396,7 @@ static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 
		return -ENOSPC;

	}



	if (parse_write_buffer_into_params(wr_buf, size,

	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,

					    (long *)param, buf,

					    max_param_num,

					    &param_nums)) {
@@ -1581,7 +1581,7 @@ static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 
		return -ENOSPC;

	}



	if (parse_write_buffer_into_params(wr_buf, size,

	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,

					    (long *)param, buf,

					    max_param_num,

					    &param_nums)) {
@@ -1766,7 +1766,7 @@ static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 
		return -ENOSPC;

	}



	if (parse_write_buffer_into_params(wr_buf, size,

	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,

					    (long *)param, buf,

					    max_param_num,

					    &param_nums)) {
@@ -1944,7 +1944,7 @@ static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *bu 
		return -ENOSPC;

	}



	if (parse_write_buffer_into_params(wr_buf, size,

	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,

					    (long *)param, buf,

					    max_param_num,

					    &param_nums)) {
@@ -2382,7 +2382,7 @@ static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 
		return -ENOSPC;

	}



	if (parse_write_buffer_into_params(wr_buf, size,

	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,

					   (long *)param, buf,

					   max_param_num,

					   &param_nums)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

+18 −11
Original line number Diff line number Diff line
@@ -366,32 +366,32 @@ static struct wm_table lpddr5_wm_table = { 
			.wm_inst = WM_A,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 5.32,

			.sr_enter_plus_exit_time_us = 6.38,

			.sr_exit_time_us = 11.5,

			.sr_enter_plus_exit_time_us = 14.5,

			.valid = true,

		},

		{

			.wm_inst = WM_B,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 9.82,

			.sr_enter_plus_exit_time_us = 11.196,

			.sr_exit_time_us = 11.5,

			.sr_enter_plus_exit_time_us = 14.5,

			.valid = true,

		},

		{

			.wm_inst = WM_C,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 9.89,

			.sr_enter_plus_exit_time_us = 11.24,

			.sr_exit_time_us = 11.5,

			.sr_enter_plus_exit_time_us = 14.5,

			.valid = true,

		},

		{

			.wm_inst = WM_D,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 9.748,

			.sr_enter_plus_exit_time_us = 11.102,

			.sr_exit_time_us = 11.5,

			.sr_enter_plus_exit_time_us = 14.5,

			.valid = true,

		},

	}
@@ -518,14 +518,21 @@ static unsigned int find_clk_for_voltage( 
		unsigned int voltage)

{

	int i;

	int max_voltage = 0;

	int clock = 0;



	for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {

		if (clock_table->SocVoltage[i] == voltage)

		if (clock_table->SocVoltage[i] == voltage) {

			return clocks[i];

		} else if (clock_table->SocVoltage[i] >= max_voltage &&

				clock_table->SocVoltage[i] < voltage) {

			max_voltage = clock_table->SocVoltage[i];

			clock = clocks[i];

		}

	}



	ASSERT(0);

	return 0;

	ASSERT(clock);

	return clock;

}



void dcn31_clk_mgr_helper_populate_bw_params(

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c

+3 −4
Original line number Diff line number Diff line
@@ -76,10 +76,6 @@ void dcn31_init_hw(struct dc *dc) 
	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);



	// Initialize the dccg

	if (res_pool->dccg->funcs->dccg_init)

		res_pool->dccg->funcs->dccg_init(res_pool->dccg);



	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {



		REG_WRITE(REFCLK_CNTL, 0);
@@ -106,6 +102,9 @@ void dcn31_init_hw(struct dc *dc) 
		hws->funcs.bios_golden_init(dc);

		hws->funcs.disable_vga(dc->hwseq);

	}

	// Initialize the dccg

	if (res_pool->dccg->funcs->dccg_init)

		res_pool->dccg->funcs->dccg_init(res_pool->dccg);



	if (dc->debug.enable_mem_low_power.bits.dmcu) {

		// Force ERAM to shutdown if DMCU is not enabled