Commit f30f5515 authored May 27, 2021 by Bindu Ramamurthy Committed by Alex Deucher Jul 21, 2021

drm/amd/display: Populate socclk entries for dcn3.02/3.03



[Why]
Initialize socclk entries in bandwidth params for dcn302, dcn303.

[How]
Fetch the sockclk values from smu for the DPM levels and for the DPM
levels where smu returns 0, previous level values are reported.

Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent d7940911

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -190,6 +190,10 @@ void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
		&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
		&num_levels);

		/* SOCCLK */
		dcn3_init_single_clock(clk_mgr, PPCLK_SOCCLK,
		&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
		&num_levels);
		// DPREFCLK ???

		/* DISPCLK */

drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c

+5 −2

Original line number	Diff line number	Diff line
		@@ -1399,10 +1399,13 @@ void dcn302_update_bw_bounding_box(struct dc dc, struct clk_bw_params bw_param
		dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
		dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
		dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz;
		if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
		dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz;
		else
		dcn3_02_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
		/* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */
		/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
		/* FCLK, PHYCLK_D18, DSCCLK */
		dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz;
		dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[0].socclk_mhz;
		dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz;
		}
		/* re-init DML with updated bb */

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c

+5 −2

Original line number	Diff line number	Diff line
		@@ -1327,10 +1327,13 @@ void dcn303_update_bw_bounding_box(struct dc dc, struct clk_bw_params bw_param
		dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
		dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
		dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz;
		if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
		dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[i-1].socclk_mhz;
		else
		dcn3_03_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
		/* These clocks cannot come from bw_params, always fill from dcn3_03_soc[1] */
		/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
		/* FCLK, PHYCLK_D18, DSCCLK */
		dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz;
		dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[0].socclk_mhz;
		dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz;
		}
		/* re-init DML with updated bb */