Commit f2ef6a91 authored by Thierry Reding's avatar Thierry Reding
Browse files

arm64: tegra: Sort Tegra210 XUSB clocks correctly 



Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 28a44b90

arch/arm64/boot/dts/nvidia/tegra210.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -1026,8 +1026,8 @@ 
			 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,

			 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,

			 <&tegra_car TEGRA210_CLK_XUSB_SS>,

			 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,

			 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,

			 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,

			 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,

			 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,

			 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
@@ -1035,7 +1035,7 @@ 
			 <&tegra_car TEGRA210_CLK_PLL_E>;

		clock-names = "xusb_host", "xusb_host_src",

			      "xusb_falcon_src", "xusb_ss",

			      "xusb_ss_src", "xusb_ss_div2",

			      "xusb_ss_div2", "xusb_ss_src",

			      "xusb_hs_src", "xusb_fs_src",

			      "pll_u_480m", "clk_m", "pll_e";

		resets = <&tegra_car 89>, <&tegra_car 156>,