Commit f2dd3669 authored by Chanho Park's avatar Chanho Park Committed by Sylwester Nawrocki
Browse files

clk: samsung: exynosautov9: add cmu_peric0 clock support 



CMU_PERIC0 provides clocks for USI0 ~ USI5 and USIx_I2C. USI0/1/2/3/4/5
have its own divider but USI_I2Cs share "dout_peric0_usi_i2c" divider.

Signed-off-by: default avatarChanho Park <chanho61.park@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220504075154.58819-9-chanho61.park@samsung.com
parent 65165b11

drivers/clk/samsung/clk-exynosautov9.c

+254 −0
Original line number Diff line number Diff line
@@ -1134,6 +1134,257 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = { 
	.clk_name		= "dout_clkcmu_fsys2_bus",

};



/* ---- CMU_PERIC0 --------------------------------------------------------- */



/* Register Offset definitions for CMU_PERIC0 (0x10200000) */

#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER	0x0600

#define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER	0x0610

#define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI	0x1000

#define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI	0x1004

#define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI	0x1008

#define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI	0x100c

#define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI	0x1010

#define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI	0x1014

#define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C	0x1018

#define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI	0x1800

#define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI	0x1804

#define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI	0x1808

#define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI	0x180c

#define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI	0x1810

#define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI	0x1814

#define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C	0x1818

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0	0x2014

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1	0x2018

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2	0x2024

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3	0x2028

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4	0x202c

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5	0x2030

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6	0x2034

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7	0x2038

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8	0x203c

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9	0x2040

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10	0x201c

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11	0x2020

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0	0x2044

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1	0x2048

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2	0x2058

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3	0x205c

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4	0x2060

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7	0x206c

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5	0x2064

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6	0x2068

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8	0x2070

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9	0x2074

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10	0x204c

#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11	0x2050



static const unsigned long peric0_clk_regs[] __initconst = {

	PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,

	PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER,

	CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI,

	CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI,

	CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI,

	CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI,

	CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI,

	CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI,

	CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C,

	CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,

	CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,

	CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,

	CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,

	CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,

	CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,

	CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,

	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,

};



/* List of parent clocks for Muxes in CMU_PERIC0 */

PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_clkcmu_peric0_bus" };

PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" };

PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" };



static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {

	MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",

	    mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),

	MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user",

	    mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1),

	/* USI00 ~ USI05 */

	MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi",

	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),

	MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi",

	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),

	MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi",

	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),

	MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi",

	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),

	MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi",

	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),

	MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi",

	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),

	/* USI_I2C */

	MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c",

	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),

};



static const struct samsung_div_clock peric0_div_clks[] __initconst = {

	/* USI00 ~ USI05 */

	DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",

	    "mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",

	    "mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",

	    "mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",

	    "mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",

	    "mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",

	    "mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,

	    0, 4),

	/* USI_I2C */

	DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",

	    "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),

};



static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {

	/* IPCLK */

	GATE(CLK_GOUT_PERIC0_IPCLK_0, "gout_peric0_ipclk_0",

	     "dout_peric0_usi00_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_IPCLK_1, "gout_peric0_ipclk_1",

	     "dout_peric0_usi_i2c",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_IPCLK_2, "gout_peric0_ipclk_2",

	     "dout_peric0_usi01_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_IPCLK_3, "gout_peric0_ipclk_3",

	     "dout_peric0_usi_i2c",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_IPCLK_4, "gout_peric0_ipclk_4",

	     "dout_peric0_usi02_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_IPCLK_5, "gout_peric0_ipclk_5",

	     "dout_peric0_usi_i2c",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_IPCLK_6, "gout_peric0_ipclk_6",

	     "dout_peric0_usi03_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_IPCLK_7, "gout_peric0_ipclk_7",

	     "dout_peric0_usi_i2c",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_IPCLK_8, "gout_peric0_ipclk_8",

	     "dout_peric0_usi04_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_IPCLK_9, "gout_peric0_ipclk_9",

	     "dout_peric0_usi_i2c",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_IPCLK_10, "gout_peric0_ipclk_10",

	     "dout_peric0_usi05_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_IPCLK_11, "gout_peric0_ipclk_11",

	     "dout_peric0_usi_i2c",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,

	     21, 0, 0),



	/* PCLK */

	GATE(CLK_GOUT_PERIC0_PCLK_0, "gout_peric0_pclk_0",

	     "mout_peric0_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2",

	     "mout_peric0_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_PCLK_3, "gout_peric0_pclk_3",

	     "mout_peric0_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_PCLK_4, "gout_peric0_pclk_4",

	     "mout_peric0_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_PCLK_5, "gout_peric0_pclk_5",

	     "mout_peric0_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_PCLK_6, "gout_peric0_pclk_6",

	     "mout_peric0_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_PCLK_7, "gout_peric0_pclk_7",

	     "mout_peric0_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_PCLK_8, "gout_peric0_pclk_8",

	     "mout_peric0_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_PCLK_9, "gout_peric0_pclk_9",

	     "mout_peric0_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_PCLK_10, "gout_peric0_pclk_10",

	     "mout_peric0_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC0_PCLK_11, "gout_peric0_pclk_11",

	     "mout_peric0_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,

	     21, 0, 0),

};



static const struct samsung_cmu_info peric0_cmu_info __initconst = {

	.mux_clks		= peric0_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(peric0_mux_clks),

	.div_clks		= peric0_div_clks,

	.nr_div_clks		= ARRAY_SIZE(peric0_div_clks),

	.gate_clks		= peric0_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(peric0_gate_clks),

	.nr_clk_ids		= PERIC0_NR_CLK,

	.clk_regs		= peric0_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(peric0_clk_regs),

	.clk_name		= "dout_clkcmu_peric0_bus",

};



/* ---- CMU_PERIS ---------------------------------------------------------- */



/* Register Offset definitions for CMU_PERIS (0x10020000) */
@@ -1202,6 +1453,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = { 
	}, {

		.compatible = "samsung,exynosautov9-cmu-fsys2",

		.data = &fsys2_cmu_info,

	}, {

		.compatible = "samsung,exynosautov9-cmu-peric0",

		.data = &peric0_cmu_info,

	}, {

		.compatible = "samsung,exynosautov9-cmu-peris",

		.data = &peris_cmu_info,