Commit f2ca92d0 authored by Sunil V L's avatar Sunil V L Committed by Rafael J. Wysocki
Browse files

ACPICA: MADT: Add RISC-V INTC interrupt controller 

ACPICA commit bd6d1ae1e13abe78e149c8b61b4bc7bc7feab015

The ECR to add RISC-V INTC interrupt controller is approved by
the UEFI forum and will be available in the next revision of
the ACPI specification.

Link: https://github.com/acpica/acpica/commit/bd6d1ae1


Signed-off-by: default avatarSunil V L <sunilvl@ventanamicro.com>
Signed-off-by: default avatarBob Moore <robert.moore@intel.com>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent 520d4a0e

include/acpi/actbl2.h

+20 −1
Original line number Diff line number Diff line
@@ -891,7 +891,8 @@ enum acpi_madt_type { 
	ACPI_MADT_TYPE_MSI_PIC = 21,

	ACPI_MADT_TYPE_BIO_PIC = 22,

	ACPI_MADT_TYPE_LPC_PIC = 23,

	ACPI_MADT_TYPE_RESERVED = 24,	/* 24 to 0x7F are reserved */

	ACPI_MADT_TYPE_RINTC = 24,

	ACPI_MADT_TYPE_RESERVED = 25,	/* 25 to 0x7F are reserved */

	ACPI_MADT_TYPE_OEM_RESERVED = 0x80	/* 0x80 to 0xFF are reserved for OEM use */

};
@@ -1251,6 +1252,24 @@ enum acpi_madt_lpc_pic_version { 
	ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */

};



/* 24: RISC-V INTC */

struct acpi_madt_rintc {

	struct acpi_subtable_header header;

	u8 version;

	u8 reserved;

	u32 flags;

	u64 hart_id;

	u32 uid;		/* ACPI processor UID */

};



/* Values for RISC-V INTC Version field above */



enum acpi_madt_rintc_version {

	ACPI_MADT_RINTC_VERSION_NONE = 0,

	ACPI_MADT_RINTC_VERSION_V1 = 1,

	ACPI_MADT_RINTC_VERSION_RESERVED = 2	/* 2 and greater are reserved */

};



/* 80: OEM data */



struct acpi_madt_oem_data {