Commit f2b4f149 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

clk: qcom: gcc-msm8974: move clock parent tables down 



Rearrage clock parent tables and PLL declarations (pull parents down
and gpll4 up), so that we can use pll hw clock fields in the next
commit.

Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221204124508.1415713-5-dmitry.baryshkov@linaro.org
parent fce76007

drivers/clk/qcom/gcc-msm8974.c

+49 −49
Original line number Diff line number Diff line
@@ -32,28 +32,6 @@ enum { 
	P_GPLL4,

};



static const struct parent_map gcc_xo_gpll0_map[] = {

	{ P_XO, 0 },

	{ P_GPLL0, 1 }

};



static const char * const gcc_xo_gpll0[] = {

	"xo",

	"gpll0_vote",

};



static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {

	{ P_XO, 0 },

	{ P_GPLL0, 1 },

	{ P_GPLL4, 5 }

};



static const char * const gcc_xo_gpll0_gpll4[] = {

	"xo",

	"gpll0_vote",

	"gpll4_vote",

};



static struct clk_pll gpll0 = {

	.l_reg = 0x0004,

	.m_reg = 0x0008,
@@ -81,6 +59,55 @@ static struct clk_regmap gpll0_vote = { 
	},

};



static struct clk_pll gpll4 = {

	.l_reg = 0x1dc4,

	.m_reg = 0x1dc8,

	.n_reg = 0x1dcc,

	.config_reg = 0x1dd4,

	.mode_reg = 0x1dc0,

	.status_reg = 0x1ddc,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpll4",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_regmap gpll4_vote = {

	.enable_reg = 0x1480,

	.enable_mask = BIT(4),

	.hw.init = &(struct clk_init_data){

		.name = "gpll4_vote",

		.parent_names = (const char *[]){ "gpll4" },

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,

	},

};



static const struct parent_map gcc_xo_gpll0_map[] = {

	{ P_XO, 0 },

	{ P_GPLL0, 1 }

};



static const char * const gcc_xo_gpll0[] = {

	"xo",

	"gpll0_vote",

};



static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {

	{ P_XO, 0 },

	{ P_GPLL0, 1 },

	{ P_GPLL4, 5 }

};



static const char * const gcc_xo_gpll0_gpll4[] = {

	"xo",

	"gpll0_vote",

	"gpll4_vote",

};



static struct clk_rcg2 config_noc_clk_src = {

	.cmd_rcgr = 0x0150,

	.hid_width = 5,
@@ -144,33 +171,6 @@ static struct clk_regmap gpll1_vote = { 
	},

};



static struct clk_pll gpll4 = {

	.l_reg = 0x1dc4,

	.m_reg = 0x1dc8,

	.n_reg = 0x1dcc,

	.config_reg = 0x1dd4,

	.mode_reg = 0x1dc0,

	.status_reg = 0x1ddc,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpll4",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_regmap gpll4_vote = {

	.enable_reg = 0x1480,

	.enable_mask = BIT(4),

	.hw.init = &(struct clk_init_data){

		.name = "gpll4_vote",

		.parent_names = (const char *[]){ "gpll4" },

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,

	},

};



static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {

	F(125000000, P_GPLL0, 1, 5, 24),

	{ }