Commit f2812227 authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Bjorn Helgaas
Browse files

phy: samsung: phy-exynos-pcie: sanitize init/power_on callbacks 

The exynos-pcie driver called phy_power_on() before phy_init() for some
historical reasons. However the generic PHY framework assumes that the
proper sequence is to call phy_init() first, then phy_power_on(). The
operations done by both functions should be considered as one action and as
such they are called by the exynos-pcie driver (without doing anything
between them). The initialization is just a sequence of register writes,
which cannot be altered without breaking the hardware operation.

To match the generic PHY framework requirement, simply move all register
writes to the phy_init()/phy_exit() and drop power_on()/power_off()
callbacks. This way the driver will also work with the old (incorrect)
PHY initialization call sequence.

Link: https://lore.kernel.org/r/20220628220409.26545-1-m.szyprowski@samsung.com


Reported-by: default avatarBjorn Helgaas <helgaas@kernel.org>
Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarChanho Park <chanho61.park@samsung.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-By: default avatarVinod Koul <vkoul@kernel.org>
parent 91a773f9

drivers/phy/samsung/phy-exynos-pcie.c

+9 −16
Original line number Diff line number Diff line
@@ -51,6 +51,13 @@ static int exynos5433_pcie_phy_init(struct phy *phy) 
{

	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);



	regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,

			   BIT(0), 1);

	regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,

			   PCIE_APP_REQ_EXIT_L1_MODE, 0);

	regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,

			   PCIE_REFCLK_GATING_EN, 0);



	regmap_update_bits(ep->fsysreg,	PCIE_EXYNOS5433_PHY_COMMON_RESET,

			   PCIE_PHY_RESET, 1);

	regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
@@ -109,20 +116,7 @@ static int exynos5433_pcie_phy_init(struct phy *phy) 
	return 0;

}



static int exynos5433_pcie_phy_power_on(struct phy *phy)

{

	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);



	regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,

			   BIT(0), 1);

	regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,

			   PCIE_APP_REQ_EXIT_L1_MODE, 0);

	regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,

			   PCIE_REFCLK_GATING_EN, 0);

	return 0;

}



static int exynos5433_pcie_phy_power_off(struct phy *phy)

static int exynos5433_pcie_phy_exit(struct phy *phy)

{

	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
@@ -135,8 +129,7 @@ static int exynos5433_pcie_phy_power_off(struct phy *phy) 


static const struct phy_ops exynos5433_phy_ops = {

	.init		= exynos5433_pcie_phy_init,

	.power_on	= exynos5433_pcie_phy_power_on,

	.power_off	= exynos5433_pcie_phy_power_off,

	.exit		= exynos5433_pcie_phy_exit,

	.owner		= THIS_MODULE,

};