Commit f27647b5 authored by Marc Zyngier's avatar Marc Zyngier Committed by Paolo Bonzini
Browse files

KVM: arm64: Don't access PMSELR_EL0/PMUSERENR_EL0 when no PMU is available 



When running under a nesting hypervisor, it isn't guaranteed that
the virtual HW will include a PMU. In which case, let's not try
to access the PMU registers in the world switch, as that'd be
deadly.

Reported-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Reviewed-by: default avatarAlexandru Elisei <alexandru.elisei@arm.com>
Link: https://lore.kernel.org/r/20210209114844.3278746-3-maz@kernel.org


Message-Id: <20210305185254.3730990-6-maz@kernel.org>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 6b5b368f

arch/arm64/kernel/image-vars.h

+3 −0
Original line number Diff line number Diff line
@@ -101,6 +101,9 @@ KVM_NVHE_ALIAS(__stop___kvm_ex_table); 
/* Array containing bases of nVHE per-CPU memory regions. */

KVM_NVHE_ALIAS(kvm_arm_hyp_percpu_base);



/* PMU available static key */

KVM_NVHE_ALIAS(kvm_arm_pmu_available);



#endif /* CONFIG_KVM */



#endif /* __ARM64_KERNEL_IMAGE_VARS_H */

arch/arm64/kvm/hyp/include/hyp/switch.h

+6 −3
Original line number Diff line number Diff line
@@ -90,14 +90,17 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu) 
	 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at

	 * EL1 instead of being trapped to EL2.

	 */

	if (kvm_arm_support_pmu_v3()) {

		write_sysreg(0, pmselr_el0);

		write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);

	}

	write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);

}



static inline void __deactivate_traps_common(void)

{

	write_sysreg(0, hstr_el2);

	if (kvm_arm_support_pmu_v3())

		write_sysreg(0, pmuserenr_el0);

}