Loading arch/arm/boot/dts/meson.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -11,7 +11,7 @@ #size-cells = <1>; interrupt-parent = <&gic>; L2: l2-cache-controller@c4200000 { L2: cache-controller@c4200000 { compatible = "arm,pl310-cache"; reg = <0xc4200000 0x1000>; cache-unified; Loading arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts +1 −1 Original line number Diff line number Diff line Loading @@ -10,7 +10,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/sound/meson-aiu.h> #include "meson-gxl-s905x.dtsi" #include "meson-gxl-s805x.dtsi" / { compatible = "libretech,aml-s805x-ac", "amlogic,s805x", Loading arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +1 −1 Original line number Diff line number Diff line Loading @@ -9,7 +9,7 @@ #include <dt-bindings/input/input.h> #include "meson-gxl-s905x.dtsi" #include "meson-gxl-s805x.dtsi" / { compatible = "amlogic,p241", "amlogic,s805x", "amlogic,meson-gxl"; Loading arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi 0 → 100644 +24 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2020 BayLibre SAS * Author: Neil Armstrong <narmstrong@baylibre.com> */ #include "meson-gxl-s905x.dtsi" / { compatible = "amlogic,s805x", "amlogic,meson-gxl"; }; /* The S805X Package doesn't seem to handle the 744MHz OPP correctly */ &mali { assigned-clocks = <&clkc CLKID_MALI_0_SEL>, <&clkc CLKID_MALI_0>, <&clkc CLKID_MALI>; /* Glitch free mux */ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, <0>, /* Do Nothing */ <&clkc CLKID_MALI_0>; assigned-clock-rates = <0>, /* Do Nothing */ <666666666>, <0>; /* Do Nothing */ }; arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +5 −0 Original line number Diff line number Diff line Loading @@ -338,6 +338,11 @@ }; }; &hwrng { clocks = <&clkc CLKID_RNG0>; clock-names = "core"; }; &i2c_A { clocks = <&clkc CLKID_I2C>; }; Loading Loading
arch/arm/boot/dts/meson.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -11,7 +11,7 @@ #size-cells = <1>; interrupt-parent = <&gic>; L2: l2-cache-controller@c4200000 { L2: cache-controller@c4200000 { compatible = "arm,pl310-cache"; reg = <0xc4200000 0x1000>; cache-unified; Loading
arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts +1 −1 Original line number Diff line number Diff line Loading @@ -10,7 +10,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/sound/meson-aiu.h> #include "meson-gxl-s905x.dtsi" #include "meson-gxl-s805x.dtsi" / { compatible = "libretech,aml-s805x-ac", "amlogic,s805x", Loading
arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +1 −1 Original line number Diff line number Diff line Loading @@ -9,7 +9,7 @@ #include <dt-bindings/input/input.h> #include "meson-gxl-s905x.dtsi" #include "meson-gxl-s805x.dtsi" / { compatible = "amlogic,p241", "amlogic,s805x", "amlogic,meson-gxl"; Loading
arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi 0 → 100644 +24 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2020 BayLibre SAS * Author: Neil Armstrong <narmstrong@baylibre.com> */ #include "meson-gxl-s905x.dtsi" / { compatible = "amlogic,s805x", "amlogic,meson-gxl"; }; /* The S805X Package doesn't seem to handle the 744MHz OPP correctly */ &mali { assigned-clocks = <&clkc CLKID_MALI_0_SEL>, <&clkc CLKID_MALI_0>, <&clkc CLKID_MALI>; /* Glitch free mux */ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, <0>, /* Do Nothing */ <&clkc CLKID_MALI_0>; assigned-clock-rates = <0>, /* Do Nothing */ <666666666>, <0>; /* Do Nothing */ };
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +5 −0 Original line number Diff line number Diff line Loading @@ -338,6 +338,11 @@ }; }; &hwrng { clocks = <&clkc CLKID_RNG0>; clock-names = "core"; }; &i2c_A { clocks = <&clkc CLKID_I2C>; }; Loading