Commit f235f6ae authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Stephen Boyd
Browse files

clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks 



Various MSDC core clocks, used for multiple MSDC controller instances,
share the same parent(s): in order to add parents selection in the
mtk-sd driver to achieve an accurate clock rate for all modes, remove
the CLK_SET_RATE_PARENT flag from all MSDC clocks for all SoCs: this
will make sure that a clk_set_rate() call performed for a clock on
a secondary controller will not change the rate of a common parent,
which would result in an overclock or underclock of one of the
controllers.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: default avatarMarkus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20230516135205.372951-3-angelogioacchino.delregno@collabora.com


Tested-by: default avatarAlexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: default avatarAlexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 1775790e

drivers/clk/mediatek/clk-mt6765.c

+6 −6
Original line number Diff line number Diff line
@@ -406,15 +406,15 @@ static const struct mtk_mux top_muxes[] = { 
			CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 2, 31,

			CLK_CFG_UPDATE, 11),

	/* CLK_CFG_3 */

	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",

	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",

			msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET,

			CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12),

	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",

			CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12, 0),

	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",

			msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET,

			CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13),

	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",

			CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13, 0),

	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",

			msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET,

			CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14),

			CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14, 0),

	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,

			CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR,

			24, 2, 31, CLK_CFG_UPDATE, 15),

drivers/clk/mediatek/clk-mt6779.c

+9 −9
Original line number Diff line number Diff line
@@ -687,16 +687,16 @@ static const struct mtk_mux top_muxes[] = { 
			     0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20),

	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,

			     0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21),

	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",

	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",

				   msdc50_hclk_parents, 0x70, 0x74, 0x78,

			     16, 2, 23, 0x004, 22),

	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel",

				   16, 2, 23, 0x004, 22, 0),

	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "msdc50_0_sel",

				   msdc50_0_parents, 0x70, 0x74, 0x78,

			     24, 3, 31, 0x004, 23),

				   24, 3, 31, 0x004, 23, 0),

	/* CLK_CFG_6 */

	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel",

	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "msdc30_1_sel",

				   msdc30_1_parents, 0x80, 0x84, 0x88,

			     0, 3, 7, 0x004, 24),

				   0, 3, 7, 0x004, 24, 0),

	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,

			     0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25),

	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",

drivers/clk/mediatek/clk-mt7981-topckgen.c

+6 −6
Original line number Diff line number Diff line
@@ -310,12 +310,12 @@ static const struct mtk_mux top_muxes[] = { 
			     pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,

			     0x1C0, 7),

	/* CLK_CFG_2 */

	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",

	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",

				   emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,

			     0x1C0, 8),

	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",

				   0x1C0, 8, 0),

	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",

				   emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,

			     0x1C0, 9),

				   0x1C0, 9, 0),

	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",

				   csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,

				   0x1C0, 10,

drivers/clk/mediatek/clk-mt7986-topckgen.c

+6 −6
Original line number Diff line number Diff line
@@ -193,12 +193,12 @@ static const struct mtk_mux top_muxes[] = { 
			     pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,

			     31, 0x1C0, 7),

	/* CLK_CFG_2 */

	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",

	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",

				   emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,

			     0x1C0, 8),

	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",

				   0x1C0, 8, 0),

	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",

				   emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,

			     0x1C0, 9),

				   0x1C0, 9, 0),

	MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",

			     f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,

			     0x1C0, 10),

drivers/clk/mediatek/clk-mt8173-topckgen.c

+12 −12
Original line number Diff line number Diff line
@@ -547,17 +547,17 @@ static const struct mtk_composite top_muxes[] = { 
	MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),

	/* CLK_CFG_3 */

	MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7),

	MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents,

		 0x0070, 8, 3, 15),

	MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents,

		 0x0070, 16, 4, 23),

	MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,

		 0x0070, 24, 3, 31),

	MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents,

		 0x0070, 8, 3, 15, 0),

	MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents,

		 0x0070, 16, 4, 23, 0),

	MUX_GATE_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,

		 0x0070, 24, 3, 31, 0),

	/* CLK_CFG_4 */

	MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents,

		 0x0080, 0, 3, 7),

	MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,

		 0x0080, 8, 4, 15),

	MUX_GATE_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents,

		 0x0080, 0, 3, 7, 0),

	MUX_GATE_FLAGS(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,

		 0x0080, 8, 4, 15, 0),

	MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,

		 0x0080, 16, 2, 23),

	MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
@@ -595,8 +595,8 @@ static const struct mtk_composite top_muxes[] = { 
	MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents,

		 0x00c0, 24, 3, 31),

	/* CLK_CFG_13 */

	MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents,

		 0x00d0, 0, 3, 7),

	MUX_GATE_FLAGS(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents,

		 0x00d0, 0, 3, 7, 0),

	MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),

	MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents,

		 0x00d0, 16, 2, 23),