Unverified Commit f1f19762 authored by Tudor Ambarus's avatar Tudor Ambarus
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mtd: spi-nor: core: Update name and description of spansion_set_4byte_addr_mode 



Rename method to spi_nor_set_4byte_addr_mode_brwr and extend its
description. This method is described in JESD216 BFPT[SFDP_DWORD(16)],
BIT(28) and BIT(20).

Reviewed-by: default avatarMichael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20230331074606.3559258-4-tudor.ambarus@linaro.org


Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
parent 288df437

drivers/mtd/spi-nor/core.c

+9 −4
Original line number Diff line number Diff line
@@ -564,15 +564,20 @@ int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable) 
}



/**

 * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion

 * flashes.

 * spi_nor_set_4byte_addr_mode_brwr() - Set 4-byte address mode using

 *			SPINOR_OP_BRWR. Typically used by Spansion flashes.

 * @nor:	pointer to 'struct spi_nor'.

 * @enable:	true to enter the 4-byte address mode, false to exit the 4-byte

 *		address mode.

 *

 * 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]) is

 * used to enable/disable 4-byte address mode. When MSB is set to ‘1’, 4-byte

 * address mode is active and A[30:24] bits are don’t care. Write instruction is

 * SPINOR_OP_BRWR(17h) with 1 byte of data.

 *

 * Return: 0 on success, -errno otherwise.

 */

static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable)

static int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable)

{

	int ret;
@@ -2966,7 +2971,7 @@ static void spi_nor_init_default_params(struct spi_nor *nor) 
	struct device_node *np = spi_nor_get_flash_node(nor);



	params->quad_enable = spi_nor_sr2_bit1_quad_enable;

	params->set_4byte_addr_mode = spansion_set_4byte_addr_mode;

	params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr;

	params->otp.org = &info->otp_org;



	/* Default to 16-bit Write Status (01h) Command */