Commit f1d2a26b authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/radeon: set VM base addr using the PFP v2 



Seems to make VM flushes more stable on SI and CIK.

v2: only use the PFP on the GFX ring on CIK

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f069dc1d

drivers/gpu/drm/radeon/cik.c

+3 −2
Original line number Diff line number Diff line
@@ -5942,12 +5942,13 @@ static void cik_vm_decode_fault(struct radeon_device *rdev, 
void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)

{

	struct radeon_ring *ring = &rdev->ring[ridx];

	int usepfp = (ridx == RADEON_RING_TYPE_GFX_INDEX);



	if (vm == NULL)

		return;



	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |

	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |

				 WRITE_DATA_DST_SEL(0)));

	if (vm->id < 8) {

		radeon_ring_write(ring,
@@ -5997,7 +5998,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 
	radeon_ring_write(ring, 1 << vm->id);



	/* compute doesn't have PFP */

	if (ridx == RADEON_RING_TYPE_GFX_INDEX) {

	if (usepfp) {

		/* sync PFP to ME, otherwise we might get invalid PFP reads */

		radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

		radeon_ring_write(ring, 0x0);

drivers/gpu/drm/radeon/si.c

+1 −1
Original line number Diff line number Diff line
@@ -5013,7 +5013,7 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 


	/* write new base address */

	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |

	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |

				 WRITE_DATA_DST_SEL(0)));



	if (vm->id < 8) {