Unverified Commit f1ceb9d1 authored by Maxime Ripard's avatar Maxime Ripard
Browse files

drm/vc4: hdmi: Compute the CEC clock divider from the clock rate 



The CEC clock divider needs to output a frequency of 40kHz from the HSM
rate on the BCM2835. The driver used to have a fixed frequency for it,
but that changed for the BCM2711 and we now need to compute it
dynamically to maintain the proper rate.

Fixes: cd4cb49d ("drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate")
Reviewed-by: default avatarDave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Acked-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Tested-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Link: https://patchwork.freedesktop.org/patch/msgid/20210111142309.193441-7-maxime@cerno.tech
parent b06eecb5

drivers/gpu/drm/vc4/vc4_hdmi.c

+3 −1
Original line number Diff line number Diff line
@@ -1598,6 +1598,7 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 
{

	struct cec_connector_info conn_info;

	struct platform_device *pdev = vc4_hdmi->pdev;

	u16 clk_cnt;

	u32 value;

	int ret;
@@ -1623,8 +1624,9 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 
	 * divider: the hsm_clock rate and this divider setting will

	 * give a 40 kHz CEC clock.

	 */

	clk_cnt = clk_get_rate(vc4_hdmi->hsm_clock) / CEC_CLOCK_FREQ;

	value |= VC4_HDMI_CEC_ADDR_MASK |

		 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);

		 (clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);

	HDMI_WRITE(HDMI_CEC_CNTRL_1, value);

	ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),

					vc4_cec_irq_handler,