Commit f1c506d1 authored by Elaine Zhang's avatar Elaine Zhang Committed by Heiko Stuebner
Browse files

clk: rockchip: add clock controller for the RK3588 



Add full clock controller support RK3588.

[rebase, integrate fixes from Wyon and Finley, add missing frequencies
 to PLL lookup table, update commit message, add GATE_LINK clocks which
 downstream handles in its own driver with one DT node per clock]

Signed-off-by: default avatarWyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: default avatarFinley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-10-sebastian.reichel@collabora.com


[dropped module stuff after talking to Sebastian]
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent ada8f95b

drivers/clk/rockchip/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -99,4 +99,12 @@ config CLK_RK3568 
	default y

	help

	  Build the driver for RK3568 Clock Driver.



config CLK_RK3588

	bool "Rockchip RK3588 clock controller support"

	depends on ARM64 || COMPILE_TEST

	default y

	help

	  Build the driver for RK3588 Clock Driver.



endif

drivers/clk/rockchip/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -28,3 +28,4 @@ obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o 
obj-$(CONFIG_CLK_RK3368)        += clk-rk3368.o

obj-$(CONFIG_CLK_RK3399)        += clk-rk3399.o

obj-$(CONFIG_CLK_RK3568)	+= clk-rk3568.o

obj-$(CONFIG_CLK_RK3588)	+= clk-rk3588.o rst-rk3588.o

drivers/clk/rockchip/clk-rk3588.c

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drivers/clk/rockchip/clk.h

+48 −1
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@@ -235,6 +235,51 @@ struct clk; 
#define RK3568_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x180)

#define RK3568_PMU_SOFTRST_CON(x)	((x) * 0x4 + 0x200)



#define RK3588_PHP_CRU_BASE		0x8000

#define RK3588_PMU_CRU_BASE		0x30000

#define RK3588_BIGCORE0_CRU_BASE	0x50000

#define RK3588_BIGCORE1_CRU_BASE	0x52000

#define RK3588_DSU_CRU_BASE		0x58000



#define RK3588_PLL_CON(x)		RK2928_PLL_CON(x)

#define RK3588_MODE_CON0		0x280

#define RK3588_B0_PLL_MODE_CON0		(RK3588_BIGCORE0_CRU_BASE + 0x280)

#define RK3588_B1_PLL_MODE_CON0		(RK3588_BIGCORE1_CRU_BASE + 0x280)

#define RK3588_LPLL_MODE_CON0		(RK3588_DSU_CRU_BASE + 0x280)

#define RK3588_CLKSEL_CON(x)		((x) * 0x4 + 0x300)

#define RK3588_CLKGATE_CON(x)		((x) * 0x4 + 0x800)

#define RK3588_SOFTRST_CON(x)		((x) * 0x4 + 0xa00)

#define RK3588_GLB_CNT_TH		0xc00

#define RK3588_GLB_SRST_FST		0xc08

#define RK3588_GLB_SRST_SND		0xc0c

#define RK3588_GLB_RST_CON		0xc10

#define RK3588_GLB_RST_ST		0xc04

#define RK3588_SDIO_CON0		0xC24

#define RK3588_SDIO_CON1		0xC28

#define RK3588_SDMMC_CON0		0xC30

#define RK3588_SDMMC_CON1		0xC34



#define RK3588_PHP_CLKGATE_CON(x)	((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)

#define RK3588_PHP_SOFTRST_CON(x)	((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)



#define RK3588_PMU_PLL_CON(x)		((x) * 0x4 + RK3588_PHP_CRU_BASE)

#define RK3588_PMU_CLKSEL_CON(x)	((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)

#define RK3588_PMU_CLKGATE_CON(x)	((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)

#define RK3588_PMU_SOFTRST_CON(x)	((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)



#define RK3588_B0_PLL_CON(x)		((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)

#define RK3588_BIGCORE0_CLKSEL_CON(x)	((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)

#define RK3588_BIGCORE0_CLKGATE_CON(x)	((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)

#define RK3588_BIGCORE0_SOFTRST_CON(x)	((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)

#define RK3588_B1_PLL_CON(x)		((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)

#define RK3588_BIGCORE1_CLKSEL_CON(x)	((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)

#define RK3588_BIGCORE1_CLKGATE_CON(x)	((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)

#define RK3588_BIGCORE1_SOFTRST_CON(x)	((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)

#define RK3588_LPLL_CON(x)		((x) * 0x4 + RK3588_DSU_CRU_BASE)

#define RK3588_DSU_CLKSEL_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)

#define RK3588_DSU_CLKGATE_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)

#define RK3588_DSU_SOFTRST_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)



enum rockchip_pll_type {

	pll_rk3036,

	pll_rk3066,
@@ -394,7 +439,7 @@ struct rockchip_cpuclk_clksel { 
	u32 val;

};



#define ROCKCHIP_CPUCLK_NUM_DIVIDERS	5

#define ROCKCHIP_CPUCLK_NUM_DIVIDERS	6

#define ROCKCHIP_CPUCLK_MAX_CORES	4

struct rockchip_cpuclk_rate_table {

	unsigned long prate;
@@ -978,4 +1023,6 @@ static inline void rockchip_register_softrst(struct device_node *np, 
	return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);

}



void rk3588_rst_init(struct device_node *np, void __iomem *reg_base);



#endif

drivers/clk/rockchip/rst-rk3588.c

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