Commit f170aa51 authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Catalin Marinas
Browse files

arm64/sysreg: Rename TRBIDR_EL1 fields per auto-gen tools format 



This renames TRBIDR_EL1 register fields per auto-gen tools format without
causing any functional change in the TRBE driver.

Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: kvmarm@lists.linux.dev
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230614065949.146187-8-anshuman.khandual@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent dae169fd

arch/arm64/include/asm/el2_setup.h

+1 −1
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ 
	cbz	x0, .Lskip_trace_\@		// Skip if TraceBuffer is not present



	mrs_s	x0, SYS_TRBIDR_EL1

	and	x0, x0, TRBIDR_PROG

	and	x0, x0, TRBIDR_EL1_P

	cbnz	x0, .Lskip_trace_\@		// If TRBE is available at EL2



	mov	x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)

arch/arm64/include/asm/sysreg.h

+4 −4
Original line number Diff line number Diff line
@@ -269,10 +269,10 @@ 
#define TRBMAR_EL1_Attr_SHIFT		0

#define TRBTRG_EL1_TRG_MASK		GENMASK(31, 0)

#define TRBTRG_EL1_TRG_SHIFT		0

#define TRBIDR_FLAG			BIT(5)

#define TRBIDR_PROG			BIT(4)

#define TRBIDR_ALIGN_MASK		GENMASK(3, 0)

#define TRBIDR_ALIGN_SHIFT		0

#define TRBIDR_EL1_F			BIT(5)

#define TRBIDR_EL1_P			BIT(4)

#define TRBIDR_EL1_Align_MASK		GENMASK(3, 0)

#define TRBIDR_EL1_Align_SHIFT		0



#define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)

#define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)

arch/arm64/kvm/debug.c

+1 −1
Original line number Diff line number Diff line
@@ -333,7 +333,7 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu) 


	/* Check if we have TRBE implemented and available at the host */

	if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceBuffer_SHIFT) &&

	    !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_PROG))

	    !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_P))

		vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRBE);

}

drivers/hwtracing/coresight/coresight-trbe.h

+3 −3
Original line number Diff line number Diff line
@@ -95,17 +95,17 @@ static inline bool is_trbe_running(u64 trbsr) 


static inline bool get_trbe_flag_update(u64 trbidr)

{

	return trbidr & TRBIDR_FLAG;

	return trbidr & TRBIDR_EL1_F;

}



static inline bool is_trbe_programmable(u64 trbidr)

{

	return !(trbidr & TRBIDR_PROG);

	return !(trbidr & TRBIDR_EL1_P);

}



static inline int get_trbe_address_align(u64 trbidr)

{

	return (trbidr >> TRBIDR_ALIGN_SHIFT) & TRBIDR_ALIGN_MASK;

	return (trbidr & TRBIDR_EL1_Align_MASK) >> TRBIDR_EL1_Align_SHIFT;

}



static inline unsigned long get_trbe_write_pointer(void)