Commit f13cc01d authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer Committed by Ralf Baechle
Browse files

[MIPS] SNI: MIPS_CPU_IRQ_BASE cleanup 



Use MIPS_CPU_IRQ_BASE instead of own define.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 3dac2561

arch/mips/sni/pcimt.c

+2 −2
Original line number Diff line number Diff line
@@ -336,9 +336,9 @@ static void sni_pcimt_hwint(void) 
	u32 pending = (read_c0_cause() & read_c0_status());



	if (pending & C_IRQ5)

		do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 7);

		do_IRQ (MIPS_CPU_IRQ_BASE + 7);

	else if (pending & C_IRQ4)

		do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 6);

		do_IRQ (MIPS_CPU_IRQ_BASE + 6);

	else if (pending & C_IRQ3)

		pcimt_hwint3();

	else if (pending & C_IRQ1)

arch/mips/sni/pcit.c

+6 −6
Original line number Diff line number Diff line
@@ -276,11 +276,11 @@ static void sni_pcit_hwint(void) 
	if (pending & C_IRQ1)

		pcit_hwint1();

	else if (pending & C_IRQ2)

		do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 4);

		do_IRQ (MIPS_CPU_IRQ_BASE + 4);

	else if (pending & C_IRQ3)

		do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 5);

		do_IRQ (MIPS_CPU_IRQ_BASE + 5);

	else if (pending & C_IRQ5)

		do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 7);

		do_IRQ (MIPS_CPU_IRQ_BASE + 7);

}



static void sni_pcit_hwint_cplus(void)
@@ -290,11 +290,11 @@ static void sni_pcit_hwint_cplus(void) 
	if (pending & C_IRQ0)

		pcit_hwint0();

	else if (pending & C_IRQ2)

		do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 4);

		do_IRQ (MIPS_CPU_IRQ_BASE + 4);

	else if (pending & C_IRQ3)

		do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 5);

		do_IRQ (MIPS_CPU_IRQ_BASE + 5);

	else if (pending & C_IRQ5)

		do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 7);

		do_IRQ (MIPS_CPU_IRQ_BASE + 7);

}



void __init sni_pcit_irq_init(void)

arch/mips/sni/rm200.c

+1 −1
Original line number Diff line number Diff line
@@ -148,7 +148,7 @@ static void sni_rm200_hwint(void) 
	int irq;



	if (pending & C_IRQ5)

		do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 7);

		do_IRQ (MIPS_CPU_IRQ_BASE + 7);

	else if (pending & C_IRQ0) {

		clear_c0_status (IE_IRQ0);

		mask = *(volatile u8 *)SNI_RM200_INT_ENA_REG ^ 0x1f;

include/asm-mips/sni.h

+4 −5
Original line number Diff line number Diff line
@@ -141,10 +141,9 @@ extern unsigned int sni_brd_type; 
#define A20R_PT_TIM0_ACK        0xbc050000

#define A20R_PT_TIM1_ACK        0xbc060000



#define SNI_MIPS_IRQ_CPU_BASE   16

#define SNI_MIPS_IRQ_CPU_TIMER  (SNI_MIPS_IRQ_CPU_BASE+7)

#define SNI_MIPS_IRQ_CPU_TIMER  (MIPS_CPU_IRQ_BASE+7)



#define SNI_A20R_IRQ_BASE       SNI_MIPS_IRQ_CPU_BASE

#define SNI_A20R_IRQ_BASE       MIPS_CPU_IRQ_BASE

#define SNI_A20R_IRQ_TIMER      (SNI_A20R_IRQ_BASE+5)



#define SNI_DS1216_A20R_BASE    0xbc081ffc
@@ -155,7 +154,7 @@ extern unsigned int sni_brd_type; 
#define SNI_PCIT_INT_START      24

#define SNI_PCIT_INT_END        30



#define PCIT_IRQ_ETHERNET       (SNI_MIPS_IRQ_CPU_BASE + 5)

#define PCIT_IRQ_ETHERNET       (MIPS_CPU_IRQ_BASE + 5)

#define PCIT_IRQ_INTA           (SNI_PCIT_INT_START + 0)

#define PCIT_IRQ_INTB           (SNI_PCIT_INT_START + 1)

#define PCIT_IRQ_INTC           (SNI_PCIT_INT_START + 2)
@@ -180,7 +179,7 @@ extern unsigned int sni_brd_type; 
#define PCIMT_IRQ_EISA		29

#define PCIMT_IRQ_SCSI		30



#define PCIMT_IRQ_ETHERNET	(SNI_MIPS_IRQ_CPU_BASE+6)

#define PCIMT_IRQ_ETHERNET	(MIPS_CPU_IRQ_BASE+6)



#if 0

#define PCIMT_IRQ_TEMPERATURE	24