Commit f131a03d authored by Marc Kleine-Budde's avatar Marc Kleine-Budde
Browse files

Merge patch series "Add support for Allwinner D1 CAN controllers" 

John Watts <contact@jookia.org> says:

This patch series adds support for the Allwinner D1 CAN controllers.
It requires adding a new device tree compatible and driver support to
work around some hardware quirks.

This has been tested on the Mango Pi MQ Dual running a T113 and a
Lichee Panel 86 running a D1.

Changes in v2:
- Re-ordered patches to work with bisecting
- Fixed device tree label underscores
- Fixed email headers
- Link to v1: https://lore.kernel.org/all/20230715112523.2533742-1-contact@jookia.org

Link: https://lore.kernel.org/all/20230721221552.1973203-2-contact@jookia.org


Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parents 74dedbd7 8abb9525

Documentation/devicetree/bindings/net/can/allwinner,sun4i-a10-can.yaml

+4 −2
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ properties: 
          - const: allwinner,sun4i-a10-can

      - const: allwinner,sun4i-a10-can

      - const: allwinner,sun8i-r40-can

      - const: allwinner,sun20i-d1-can



  reg:

    maxItems: 1
@@ -37,8 +38,9 @@ properties: 
if:

  properties:

    compatible:

      contains:

        const: allwinner,sun8i-r40-can

      enum:

        - allwinner,sun8i-r40-can

        - allwinner,sun20i-d1-can



then:

  required:

arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -131,6 +131,18 @@ 
				pins = "PB6", "PB7";

				function = "uart3";

			};



			/omit-if-no-ref/

			can0_pins: can0-pins {

				pins = "PB2", "PB3";

				function = "can0";

			};



			/omit-if-no-ref/

			can1_pins: can1-pins {

				pins = "PB4", "PB5";

				function = "can1";

			};

		};



		ccu: clock-controller@2001000 {
@@ -879,5 +891,23 @@ 
			clock-names = "bus", "hosc", "ahb";

			#clock-cells = <1>;

		};



		can0: can@2504000 {

			compatible = "allwinner,sun20i-d1-can";

			reg = <0x02504000 0x400>;

			interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_CAN0>;

			resets = <&ccu RST_BUS_CAN0>;

			status = "disabled";

		};



		can1: can@2504400 {

			compatible = "allwinner,sun20i-d1-can";

			reg = <0x02504400 0x400>;

			interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_CAN1>;

			resets = <&ccu RST_BUS_CAN1>;

			status = "disabled";

		};

	};

};

drivers/net/can/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -190,10 +190,10 @@ config CAN_SLCAN 


config CAN_SUN4I

	tristate "Allwinner A10 CAN controller"

	depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST

	depends on MACH_SUN4I || MACH_SUN7I || RISCV || COMPILE_TEST

	help

	  Say Y here if you want to use CAN controller found on Allwinner

	  A10/A20 SoCs.

	  A10/A20/D1 SoCs.



	  To compile this driver as a module, choose M here: the module will

	  be called sun4i_can.

drivers/net/can/sun4i_can.c

+19 −3
Original line number Diff line number Diff line
@@ -91,6 +91,8 @@ 
#define SUN4I_REG_BUF12_ADDR	0x0070	/* CAN Tx/Rx Buffer 12 */

#define SUN4I_REG_ACPC_ADDR	0x0040	/* CAN Acceptance Code 0 */

#define SUN4I_REG_ACPM_ADDR	0x0044	/* CAN Acceptance Mask 0 */

#define SUN4I_REG_ACPC_ADDR_D1	0x0028	/* CAN Acceptance Code 0 on the D1 */

#define SUN4I_REG_ACPM_ADDR_D1	0x002C	/* CAN Acceptance Mask 0 on the D1 */

#define SUN4I_REG_RBUF_RBACK_START_ADDR	0x0180	/* CAN transmit buffer start */

#define SUN4I_REG_RBUF_RBACK_END_ADDR	0x01b0	/* CAN transmit buffer end */
@@ -205,9 +207,11 @@ 
 * struct sun4ican_quirks - Differences between SoC variants.

 *

 * @has_reset: SoC needs reset deasserted.

 * @acp_offset: Offset of ACPC and ACPM registers

 */

struct sun4ican_quirks {

	bool has_reset;

	int acp_offset;

};



struct sun4ican_priv {
@@ -216,6 +220,7 @@ struct sun4ican_priv { 
	struct clk *clk;

	struct reset_control *reset;

	spinlock_t cmdreg_lock;	/* lock for concurrent cmd register writes */

	int acp_offset;

};



static const struct can_bittiming_const sun4ican_bittiming_const = {
@@ -338,8 +343,8 @@ static int sun4i_can_start(struct net_device *dev) 
	}



	/* set filters - we accept all */

	writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR);

	writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR);

	writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR + priv->acp_offset);

	writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR + priv->acp_offset);



	/* clear error counters and error code capture */

	writel(0, priv->base + SUN4I_REG_ERRC_ADDR);
@@ -768,10 +773,17 @@ static const struct ethtool_ops sun4ican_ethtool_ops = { 


static const struct sun4ican_quirks sun4ican_quirks_a10 = {

	.has_reset = false,

	.acp_offset = 0,

};



static const struct sun4ican_quirks sun4ican_quirks_r40 = {

	.has_reset = true,

	.acp_offset = 0,

};



static const struct sun4ican_quirks sun4ican_quirks_d1 = {

	.has_reset = true,

	.acp_offset = (SUN4I_REG_ACPC_ADDR_D1 - SUN4I_REG_ACPC_ADDR),

};



static const struct of_device_id sun4ican_of_match[] = {
@@ -784,6 +796,9 @@ static const struct of_device_id sun4ican_of_match[] = { 
	}, {

		.compatible = "allwinner,sun8i-r40-can",

		.data = &sun4ican_quirks_r40

	}, {

		.compatible = "allwinner,sun20i-d1-can",

		.data = &sun4ican_quirks_d1

	}, {

		/* sentinel */

	},
@@ -870,6 +885,7 @@ static int sun4ican_probe(struct platform_device *pdev) 
	priv->base = addr;

	priv->clk = clk;

	priv->reset = reset;

	priv->acp_offset = quirks->acp_offset;

	spin_lock_init(&priv->cmdreg_lock);



	platform_set_drvdata(pdev, dev);
@@ -907,4 +923,4 @@ module_platform_driver(sun4i_can_driver); 
MODULE_AUTHOR("Peter Chen <xingkongcp@gmail.com>");

MODULE_AUTHOR("Gerhard Bertelsmann <info@gerhard-bertelsmann.de>");

MODULE_LICENSE("Dual BSD/GPL");

MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20)");
 
MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20/D1)");