Commit f0fae8a0 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-5.18' of... 

Merge tag 'irqchip-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates from Marc Zyngier:

  - Add support for the STM32MP13 variant

  - Move parent device away from struct irq_chip

  - Remove all instances of non-const strings assigned to
    struct irq_chip::name, enabling a nice cleanup for VIC and GIC)

  - Simplify the Qualcomm PDC driver

  - A bunch of SiFive PLIC cleanups

  - Add support for a new variant of the Meson GPIO block

  - Add support for the irqchip side of the Apple M1 PMU

  - Add support for the Apple M1 Pro/Max AICv2 irqchip

  - Add support for the Qualcomm MPM wakeup gadget

  - Move the Xilinx driver over to the generic irqdomain handling

  - Tiny speedup for IPIs on GICv3 systems

  - The usual odd cleanups

Link: https://lore.kernel.org/all/20220313105142.704579-1-maz@kernel.org
parents ff8dcfeb de26a742

Documentation/devicetree/bindings/arm/pmu.yaml

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@@ -20,6 +20,8 @@ properties: 
    items:

      - enum:

          - apm,potenza-pmu

          - apple,firestorm-pmu

          - apple,icestorm-pmu

          - arm,armv8-pmuv3 # Only for s/w models

          - arm,arm1136-pmu

          - arm,arm1176-pmu

Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

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@@ -18,6 +18,7 @@ Required properties: 
    "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)

    "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)

    "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)

    "amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : Specifies the number of cells needed to encode an

Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml

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@@ -56,6 +56,8 @@ properties: 
          - 1: virtual HV timer

          - 2: physical guest timer

          - 3: virtual guest timer

          - 4: 'efficient' CPU PMU

          - 5: 'performance' CPU PMU



      The 3rd cell contains the interrupt flags. This is normally

      IRQ_TYPE_LEVEL_HIGH (4).
@@ -68,6 +70,35 @@ properties: 
  power-domains:

    maxItems: 1



  affinities:

    type: object

    additionalProperties: false

    description:

      FIQ affinity can be expressed as a single "affinities" node,

      containing a set of sub-nodes, one per FIQ with a non-default

      affinity.

    patternProperties:

      "^.+-affinity$":

        type: object

        additionalProperties: false

        properties:

          apple,fiq-index:

            description:

              The interrupt number specified as a FIQ, and for which

              the affinity is not the default.

            $ref: /schemas/types.yaml#/definitions/uint32

            maximum: 5



          cpus:

            $ref: /schemas/types.yaml#/definitions/phandle-array

            description:

              Should be a list of phandles to CPU nodes (as described in

              Documentation/devicetree/bindings/arm/cpus.yaml).



        required:

          - fiq-index

          - cpus



required:

  - compatible

  - '#interrupt-cells'

Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Apple Interrupt Controller 2



maintainers:

  - Hector Martin <marcan@marcan.st>



description: |

  The Apple Interrupt Controller 2 is a simple interrupt controller present on

  Apple ARM SoC platforms starting with t600x (M1 Pro and Max).



  It provides the following features:



  - Level-triggered hardware IRQs wired to SoC blocks

    - Single mask bit per IRQ

    - Automatic masking on event delivery (auto-ack)

    - Software triggering (ORed with hw line)

  - Automatic prioritization (single event/ack register per CPU, lower IRQs =

    higher priority)

  - Automatic masking on ack

  - Support for multiple dies



  This device also represents the FIQ interrupt sources on platforms using AIC,

  which do not go through a discrete interrupt controller. It also handles

  FIQ-based Fast IPIs.



properties:

  compatible:

    items:

      - const: apple,t6000-aic

      - const: apple,aic2



  interrupt-controller: true



  '#interrupt-cells':

    const: 4

    description: |

      The 1st cell contains the interrupt type:

        - 0: Hardware IRQ

        - 1: FIQ



      The 2nd cell contains the die ID.



      The next cell contains the interrupt number.

        - HW IRQs: interrupt number

        - FIQs:

          - 0: physical HV timer

          - 1: virtual HV timer

          - 2: physical guest timer

          - 3: virtual guest timer



      The last cell contains the interrupt flags. This is normally

      IRQ_TYPE_LEVEL_HIGH (4).



  reg:

    items:

      - description: Address and size of the main AIC2 registers.

      - description: Address and size of the AIC2 Event register.



  reg-names:

    items:

      - const: core

      - const: event



  power-domains:

    maxItems: 1



required:

  - compatible

  - '#interrupt-cells'

  - interrupt-controller

  - reg

  - reg-names



additionalProperties: false



allOf:

  - $ref: /schemas/interrupt-controller.yaml#



examples:

  - |

    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        aic: interrupt-controller@28e100000 {

            compatible = "apple,t6000-aic", "apple,aic2";

            #interrupt-cells = <4>;

            interrupt-controller;

            reg = <0x2 0x8e100000 0x0 0xc000>,

                  <0x2 0x8e10c000 0x0 0x4>;

            reg-names = "core", "event";

        };

    };

Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcom MPM Interrupt Controller



maintainers:

  - Shawn Guo <shawn.guo@linaro.org>



description:

  Qualcomm Technologies Inc. SoCs based on the RPM architecture have a

  MSM Power Manager (MPM) that is in always-on domain. In addition to managing

  resources during sleep, the hardware also has an interrupt controller that

  monitors the interrupts when the system is asleep, wakes up the APSS when

  one of these interrupts occur and replays it to GIC interrupt controller

  after GIC becomes operational.



allOf:

  - $ref: /schemas/interrupt-controller.yaml#



properties:

  compatible:

    items:

      - const: qcom,mpm



  reg:

    maxItems: 1

    description:

      Specifies the base address and size of vMPM registers in RPM MSG RAM.



  interrupts:

    maxItems: 1

    description:

      Specify the IRQ used by RPM to wakeup APSS.



  mboxes:

    maxItems: 1

    description:

      Specify the mailbox used to notify RPM for writing vMPM registers.



  interrupt-controller: true



  '#interrupt-cells':

    const: 2

    description:

      The first cell is the MPM pin number for the interrupt, and the second

      is the trigger type.



  qcom,mpm-pin-count:

    description:

      Specify the total MPM pin count that a SoC supports.

    $ref: /schemas/types.yaml#/definitions/uint32



  qcom,mpm-pin-map:

    description:

      A set of MPM pin numbers and the corresponding GIC SPIs.

    $ref: /schemas/types.yaml#/definitions/uint32-matrix

    items:

      items:

        - description: MPM pin number

        - description: GIC SPI number for the MPM pin



required:

  - compatible

  - reg

  - interrupts

  - mboxes

  - interrupt-controller

  - '#interrupt-cells'

  - qcom,mpm-pin-count

  - qcom,mpm-pin-map



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mpm: interrupt-controller@45f01b8 {

        compatible = "qcom,mpm";

        interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;

        reg = <0x45f01b8 0x1000>;

        mboxes = <&apcs_glb 1>;

        interrupt-controller;

        #interrupt-cells = <2>;

        interrupt-parent = <&intc>;

        qcom,mpm-pin-count = <96>;

        qcom,mpm-pin-map = <2 275>,

                           <5 296>,

                           <12 422>,

                           <24 79>,

                           <86 183>,

                           <90 260>,

                           <91 260>;

    };