Commit f0f32e7d authored Sep 29, 2024 by Aichun Shi

Enable CONFIG_PCIE_EDR in openeuler_defconfig for x86

Intel inclusion
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/IAUK5F


CVE: N/A

-------------------------------------

Enable CONFIG_PCIE_EDR in openeuler_defconfig for x86 to enable PCIe
eDPC feature.

Intel-SIG: openeuler_defconfig: Enable CONFIG_PCIE_EDR in
openeuler_defconfig for x86
Support for PCIe eDPC feature

Signed-off-by: Aichun Shi <aichun.shi@intel.com>

parent 0988d5e5

arch/x86/configs/openeuler_defconfig

+1 −1

Original line number	Diff line number	Diff line
		@@ -1964,7 +1964,7 @@ CONFIG_PCIEASPM_DEFAULT=y
		CONFIG_PCIE_PME=y
		CONFIG_PCIE_DPC=y
		# CONFIG_PCIE_PTM is not set
		# CONFIG_PCIE_EDR is not set
		CONFIG_PCIE_EDR=y
		CONFIG_PCI_MSI=y
		CONFIG_PCI_MSI_IRQ_DOMAIN=y
		CONFIG_PCI_QUIRKS=y