Commit f0e12668 authored by Thierry Reding's avatar Thierry Reding
Browse files

arm64: tegra: Add main and AON GPIO controllers on Tegra234 



These two controllers expose general purpose I/O pins that can be used
to control or monitor a variety of signals.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 06ad2ec4

arch/arm64/boot/dts/nvidia/tegra234.dtsi

+74 −0
Original line number Diff line number Diff line
@@ -25,6 +25,65 @@ 
			status = "okay";

		};



		gpio: gpio@2200000 {

			compatible = "nvidia,tegra234-gpio";

			reg-names = "security", "gpio";

			reg = <0x02200000 0x10000>,

			      <0x02210000 0x10000>;

			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;

			#interrupt-cells = <2>;

			interrupt-controller;

			#gpio-cells = <2>;

			gpio-controller;

		};



		uarta: serial@3100000 {

			compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";

			reg = <0x03100000 0x10000>;
@@ -111,6 +170,21 @@ 
			status = "disabled";

		};



		gpio_aon: gpio@c2f0000 {

			compatible = "nvidia,tegra234-gpio-aon";

			reg-names = "security", "gpio";

			reg = <0x0c2f0000 0x1000>,

			      <0x0c2f1000 0x1000>;

			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;

			#interrupt-cells = <2>;

			interrupt-controller;

			#gpio-cells = <2>;

			gpio-controller;

		};



		pmc: pmc@c360000 {

			compatible = "nvidia,tegra234-pmc";

			reg = <0x0c360000 0x10000>,