Commit f0c00454 authored by Biju Das's avatar Biju Das Committed by Ulf Hansson
Browse files

mmc: renesas_sdhi: Fix rounding errors 



Due to clk rounding errors on RZ/G2L platforms, it selects a clock source
with a lower clock rate compared to a higher one.
For eg: The rounding error (533333333 Hz / 4 * 4 = 533333332 Hz < 5333333
33 Hz) selects a clk source of 400 MHz instead of 533.333333 MHz.

This patch fixes this issue by adding a margin of (1/1024) higher to
the clock rate.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Tested-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Fixes: bb6d3fa9 ("clk: renesas: rcar-gen3: Switch to new SD clock handling")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220928110755.849275-1-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 07d2872b

drivers/mmc/host/renesas_sdhi_core.c

+18 −3
Original line number Diff line number Diff line
@@ -128,6 +128,7 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 
	struct clk *ref_clk = priv->clk;

	unsigned int freq, diff, best_freq = 0, diff_min = ~0;

	unsigned int new_clock, clkh_shift = 0;

	unsigned int new_upper_limit;

	int i;



	/*
@@ -153,13 +154,20 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 
	 * greater than, new_clock.  As we can divide by 1 << i for

	 * any i in [0, 9] we want the input clock to be as close as

	 * possible, but no greater than, new_clock << i.

	 *

	 * Add an upper limit of 1/1024 rate higher to the clock rate to fix

	 * clk rate jumping to lower rate due to rounding error (eg: RZ/G2L has

	 * 3 clk sources 533.333333 MHz, 400 MHz and 266.666666 MHz. The request

	 * for 533.333333 MHz will selects a slower 400 MHz due to rounding

	 * error (533333333 Hz / 4 * 4 = 533333332 Hz < 533333333 Hz)).

	 */

	for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {

		freq = clk_round_rate(ref_clk, new_clock << i);

		if (freq > (new_clock << i)) {

		new_upper_limit = (new_clock << i) + ((new_clock << i) >> 10);

		if (freq > new_upper_limit) {

			/* Too fast; look for a slightly slower option */

			freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3);

			if (freq > (new_clock << i))

			if (freq > new_upper_limit)

				continue;

		}
@@ -181,6 +189,7 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 
static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,

				   unsigned int new_clock)

{

	unsigned int clk_margin;

	u32 clk = 0, clock;



	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
@@ -194,7 +203,13 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 
	host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);

	clock = host->mmc->actual_clock / 512;



	for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)

	/*

	 * Add a margin of 1/1024 rate higher to the clock rate in order

	 * to avoid clk variable setting a value of 0 due to the margin

	 * provided for actual_clock in renesas_sdhi_clk_update().

	 */

	clk_margin = new_clock >> 10;

	for (clk = 0x80000080; new_clock + clk_margin >= (clock << 1); clk >>= 1)

		clock <<= 1;



	/* 1/1 clock is option */