Commit f0b29707 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915: Nuke not needed members of dram_info 



Valid, ranks and bandwidth_kbps are set into dram_info but are not
used anywhere else so nuking it.

Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210128164312.91160-1-jose.souza@intel.com
parent b59c27ca

drivers/gpu/drm/i915/i915_drv.c

+2 −2
Original line number Diff line number Diff line
@@ -610,8 +610,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 


	intel_opregion_setup(dev_priv);

	/*

	 * Fill the dram structure to get the system raw bandwidth and

	 * dram info. This will be used for memory latency calculation.

	 * Fill the dram structure to get the system dram info. This will be

	 * used for memory latency calculation.

	 */

	intel_dram_detect(dev_priv);

drivers/gpu/drm/i915/i915_drv.h

+0 −3
Original line number Diff line number Diff line
@@ -1125,11 +1125,8 @@ struct drm_i915_private { 
	} wm;



	struct dram_info {

		bool valid;

		bool is_16gb_dimm;

		u8 num_channels;

		u8 ranks;

		u32 bandwidth_kbps;

		bool symmetric_memory;

		enum intel_dram_type {

			INTEL_DRAM_UNKNOWN,

drivers/gpu/drm/i915/intel_dram.c

+10 −37
Original line number Diff line number Diff line
@@ -201,17 +201,7 @@ skl_dram_get_channels_info(struct drm_i915_private *i915) 
		return -EINVAL;

	}



	/*

	 * If any of the channel is single rank channel, worst case output

	 * will be same as if single rank memory, so consider single rank

	 * memory.

	 */

	if (ch0.ranks == 1 || ch1.ranks == 1)

		dram_info->ranks = 1;

	else

		dram_info->ranks = max(ch0.ranks, ch1.ranks);



	if (dram_info->ranks == 0) {

	if (ch0.ranks == 0 && ch1.ranks == 0) {

		drm_info(&i915->drm, "couldn't get memory rank information\n");

		return -EINVAL;

	}
@@ -269,16 +259,12 @@ skl_get_dram_info(struct drm_i915_private *i915) 
	mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *

				    SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);



	dram_info->bandwidth_kbps = dram_info->num_channels *

		mem_freq_khz * 8;



	if (dram_info->bandwidth_kbps == 0) {

	if (dram_info->num_channels * mem_freq_khz == 0) {

		drm_info(&i915->drm,

			 "Couldn't get system memory bandwidth\n");

		return -EINVAL;

	}



	dram_info->valid = true;

	return 0;

}
@@ -365,7 +351,7 @@ static int bxt_get_dram_info(struct drm_i915_private *i915) 
	struct dram_info *dram_info = &i915->dram_info;

	u32 dram_channels;

	u32 mem_freq_khz, val;

	u8 num_active_channels;

	u8 num_active_channels, valid_ranks = 0;

	int i;



	val = intel_uncore_read(&i915->uncore, BXT_P_CR_MC_BIOS_REQ_0_0_0);
@@ -375,10 +361,7 @@ static int bxt_get_dram_info(struct drm_i915_private *i915) 
	dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;

	num_active_channels = hweight32(dram_channels);



	/* Each active bit represents 4-byte channel */

	dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);



	if (dram_info->bandwidth_kbps == 0) {

	if (mem_freq_khz * num_active_channels == 0) {

		drm_info(&i915->drm,

			 "Couldn't get system memory bandwidth\n");

		return -EINVAL;
@@ -410,27 +393,18 @@ static int bxt_get_dram_info(struct drm_i915_private *i915) 
			    dimm.size, dimm.width, dimm.ranks,

			    intel_dram_type_str(type));



		/*

		 * If any of the channel is single rank channel,

		 * worst case output will be same as if single rank

		 * memory, so consider single rank memory.

		 */

		if (dram_info->ranks == 0)

			dram_info->ranks = dimm.ranks;

		else if (dimm.ranks == 1)

			dram_info->ranks = 1;

		if (valid_ranks == 0)

			valid_ranks = dimm.ranks;



		if (type != INTEL_DRAM_UNKNOWN)

			dram_info->type = type;

	}



	if (dram_info->type == INTEL_DRAM_UNKNOWN || dram_info->ranks == 0) {

	if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) {

		drm_info(&i915->drm, "couldn't get memory information\n");

		return -EINVAL;

	}



	dram_info->valid = true;



	return 0;

}
@@ -456,11 +430,10 @@ void intel_dram_detect(struct drm_i915_private *i915) 
	if (ret)

		return;



	drm_dbg_kms(&i915->drm, "DRAM bandwidth: %u kBps, channels: %u\n",

		    dram_info->bandwidth_kbps, dram_info->num_channels);

	drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);



	drm_dbg_kms(&i915->drm, "DRAM ranks: %u, 16Gb DIMMs: %s\n",

		    dram_info->ranks, yesno(dram_info->is_16gb_dimm));

	drm_dbg_kms(&i915->drm, "DRAM 16Gb DIMMs: %s\n",

		    yesno(dram_info->is_16gb_dimm));

}



static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)