Loading include/dt-bindings/clock/axg-clkc.h +25 −0 Original line number Diff line number Diff line Loading @@ -72,5 +72,30 @@ #define CLKID_PCIE_CML_EN1 80 #define CLKID_MIPI_ENABLE 81 #define CLKID_GEN_CLK 84 #define CLKID_VPU_0_SEL 92 #define CLKID_VPU_0 93 #define CLKID_VPU_1_SEL 95 #define CLKID_VPU_1 96 #define CLKID_VPU 97 #define CLKID_VAPB_0_SEL 99 #define CLKID_VAPB_0 100 #define CLKID_VAPB_1_SEL 102 #define CLKID_VAPB_1 103 #define CLKID_VAPB_SEL 104 #define CLKID_VAPB 105 #define CLKID_VCLK 106 #define CLKID_VCLK2 107 #define CLKID_VCLK_DIV1 122 #define CLKID_VCLK_DIV2 123 #define CLKID_VCLK_DIV4 124 #define CLKID_VCLK_DIV6 125 #define CLKID_VCLK_DIV12 126 #define CLKID_VCLK2_DIV1 127 #define CLKID_VCLK2_DIV2 128 #define CLKID_VCLK2_DIV4 129 #define CLKID_VCLK2_DIV6 130 #define CLKID_VCLK2_DIV12 131 #define CLKID_CTS_ENCL 133 #define CLKID_VDIN_MEAS 136 #endif /* __AXG_CLKC_H */ Loading
include/dt-bindings/clock/axg-clkc.h +25 −0 Original line number Diff line number Diff line Loading @@ -72,5 +72,30 @@ #define CLKID_PCIE_CML_EN1 80 #define CLKID_MIPI_ENABLE 81 #define CLKID_GEN_CLK 84 #define CLKID_VPU_0_SEL 92 #define CLKID_VPU_0 93 #define CLKID_VPU_1_SEL 95 #define CLKID_VPU_1 96 #define CLKID_VPU 97 #define CLKID_VAPB_0_SEL 99 #define CLKID_VAPB_0 100 #define CLKID_VAPB_1_SEL 102 #define CLKID_VAPB_1 103 #define CLKID_VAPB_SEL 104 #define CLKID_VAPB 105 #define CLKID_VCLK 106 #define CLKID_VCLK2 107 #define CLKID_VCLK_DIV1 122 #define CLKID_VCLK_DIV2 123 #define CLKID_VCLK_DIV4 124 #define CLKID_VCLK_DIV6 125 #define CLKID_VCLK_DIV12 126 #define CLKID_VCLK2_DIV1 127 #define CLKID_VCLK2_DIV2 128 #define CLKID_VCLK2_DIV4 129 #define CLKID_VCLK2_DIV6 130 #define CLKID_VCLK2_DIV12 131 #define CLKID_CTS_ENCL 133 #define CLKID_VDIN_MEAS 136 #endif /* __AXG_CLKC_H */