Unverified Commit f055268e authored by Heiko Stuebner's avatar Heiko Stuebner Committed by Palmer Dabbelt
Browse files

riscv: drop some idefs from CMO initialization 



Wrapping things in #ifdefs makes the code harder to read
while we also have IS_ENABLED() macros to do this in regular code
and the extension detection is not _that_ runtime critical.

So define a stub for riscv_noncoherent_supported() in the
non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to
us IS_ENABLED.

Suggested-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Reviewed-by: default avatarGuo Ren <guoren@kernel.org>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20220905111027.2463297-3-heiko@sntech.de


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent e47bddcb

arch/riscv/errata/thead/errata.c

+3 −4
Original line number Diff line number Diff line
@@ -30,7 +30,9 @@ static bool errata_probe_pbmt(unsigned int stage, 
static bool errata_probe_cmo(unsigned int stage,

			     unsigned long arch_id, unsigned long impid)

{

#ifdef CONFIG_ERRATA_THEAD_CMO

	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))

		return false;



	if (arch_id != 0 || impid != 0)

		return false;
@@ -39,9 +41,6 @@ static bool errata_probe_cmo(unsigned int stage, 


	riscv_noncoherent_supported();

	return true;

#else

	return false;

#endif

}



static u32 thead_errata_probe(unsigned int stage,

arch/riscv/include/asm/cacheflush.h

+2 −0
Original line number Diff line number Diff line
@@ -50,6 +50,8 @@ static inline void riscv_init_cbom_blocksize(void) { } 


#ifdef CONFIG_RISCV_DMA_NONCOHERENT

void riscv_noncoherent_supported(void);

#else

static inline void riscv_noncoherent_supported(void) {}

#endif



/*

arch/riscv/kernel/cpufeature.c

+9 −13
Original line number Diff line number Diff line
@@ -264,21 +264,17 @@ static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage) 


static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)

{

#ifdef CONFIG_RISCV_ISA_ZICBOM

	switch (stage) {

	case RISCV_ALTERNATIVES_EARLY_BOOT:

	if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))

		return false;

	default:

		if (riscv_isa_extension_available(NULL, ZICBOM)) {

			riscv_noncoherent_supported();

			return true;

		} else {



	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)

		return false;

		}

	}

#endif



	if (!riscv_isa_extension_available(NULL, ZICBOM))

		return false;



	riscv_noncoherent_supported();

	return true;

}



/*