Commit f03eb1d2 authored by Jesse Zhang's avatar Jesse Zhang Committed by Alex Deucher
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drm/amdgpu: switch to golden tsc registers for raven/raven2 



Due to raven/raven2 maybe enable  sclk slow down,
they cannot get clock count by the RLC at the auto level of dpm performance.
So switch to golden tsc register.

Suggested-by: default avatarshanshengwang <shansheng.wang@amd.com>
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarJesse Zhang <jesse.zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6fe2ecdb

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+40 −0
Original line number Diff line number Diff line
@@ -149,6 +149,16 @@ MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); 
#define mmGOLDEN_TSC_COUNT_LOWER_Renoir                0x0026

#define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX       1



#define mmGOLDEN_TSC_COUNT_UPPER_Raven   0x007a

#define mmGOLDEN_TSC_COUNT_UPPER_Raven_BASE_IDX 0

#define mmGOLDEN_TSC_COUNT_LOWER_Raven   0x007b

#define mmGOLDEN_TSC_COUNT_LOWER_Raven_BASE_IDX 0



#define mmGOLDEN_TSC_COUNT_UPPER_Raven2   0x0068

#define mmGOLDEN_TSC_COUNT_UPPER_Raven2_BASE_IDX 0

#define mmGOLDEN_TSC_COUNT_LOWER_Raven2   0x0069

#define mmGOLDEN_TSC_COUNT_LOWER_Raven2_BASE_IDX 0



enum ta_ras_gfx_subblock {

	/*CPC*/

	TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
@@ -3988,6 +3998,36 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 
		preempt_enable();

		clock = clock_lo | (clock_hi << 32ULL);

		break;

	case IP_VERSION(9, 1, 0):

		preempt_disable();

		clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);

		clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);

		hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);

		/* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over

		 * roughly every 42 seconds.

		 */

		if (hi_check != clock_hi) {

			clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);

			clock_hi = hi_check;

		}

		preempt_enable();

		clock = clock_lo | (clock_hi << 32ULL);

		break;

	case IP_VERSION(9, 2, 2):

		preempt_disable();

		clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);

		clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);

		hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);

		/* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over

		 * roughly every 42 seconds.

		 */

		if (hi_check != clock_hi) {

			clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);

			clock_hi = hi_check;

		}

		preempt_enable();

		clock = clock_lo | (clock_hi << 32ULL);

		break;

	default:

		amdgpu_gfx_off_ctrl(adev, false);

		mutex_lock(&adev->gfx.gpu_clock_mutex);