Unverified Commit f03e9509 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.18-next-soc' of... 

Merge tag 'v5.18-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/soc

mmsys:
- add SW reset to MT8192
- add support for MT8195

pmic wrapper:
- update binding description needed for future MT8195 support

mutex:
- add support for MT8195

cmdq helper:
- remove legacy callback

* tag 'v5.18-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  soc: mediatek: mutex: remove mt8195 MOD0 and SOF0 definition
  dt-bindings: pwrap: mediatek: Update pwrap document for mt8195
  soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
  soc: mediatek: add mtk-mutex support for mt8195 vdosys0
  soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  soc: mediatek: cmdq: Use mailbox rx_callback instead of cmdq_task_cb
  dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
  dt-bindings: arm: mediatek: mmsys: add power and gce properties
  soc: mediatek: mmsys: Add sw0_rst_offset for MT8192

Link: https://lore.kernel.org/r/6412eecf-a4c3-cf06-55ff-9df8b0656d21@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 30258ae6 537f8ffb

Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml

+32 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ properties: 
              - mediatek,mt8183-mmsys

              - mediatek,mt8186-mmsys

              - mediatek,mt8192-mmsys

              - mediatek,mt8195-mmsys

              - mediatek,mt8365-mmsys

          - const: syscon

      - items:
@@ -41,6 +42,30 @@ properties: 
  reg:

    maxItems: 1



  power-domains:

    description:

      A phandle and PM domain specifier as defined by bindings

      of the power controller specified by phandle. See

      Documentation/devicetree/bindings/power/power-domain.yaml for details.



  mboxes:

    description:

      Using mailbox to communicate with GCE, it should have this

      property and list of phandle, mailbox specifiers. See

      Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.

    $ref: /schemas/types.yaml#/definitions/phandle-array



  mediatek,gce-client-reg:

    description:

      The register of client driver can be configured by gce with 4 arguments

      defined in this property, such as phandle of gce, subsys id,

      register offset and size.

      Each subsys id is mapping to a base address of display function blocks

      register which is defined in the gce header

      include/dt-bindings/gce/<chip>-gce.h.

    $ref: /schemas/types.yaml#/definitions/phandle-array

    maxItems: 1



  "#clock-cells":

    const: 1
@@ -56,9 +81,16 @@ additionalProperties: false 


examples:

  - |

    #include <dt-bindings/power/mt8173-power.h>

    #include <dt-bindings/gce/mt8173-gce.h>



    mmsys: syscon@14000000 {

        compatible = "mediatek,mt8173-mmsys", "syscon";

        reg = <0x14000000 0x1000>;

        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;

        #clock-cells = <1>;

        #reset-cells = <1>;

        mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,

                 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;

        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;

    };

Documentation/devicetree/bindings/soc/mediatek/pwrap.txt

+5 −5
Original line number Diff line number Diff line
@@ -31,20 +31,20 @@ Required properties in pwrap device node. 
	"mediatek,mt8195-pwrap" for MT8195 SoCs

	"mediatek,mt8516-pwrap" for MT8516 SoCs

- interrupts: IRQ for pwrap in SOC

- reg-names: Must include the following entries:

- reg-names: "pwrap" is required; "pwrap-bridge" is optional.

  "pwrap": Main registers base

  "pwrap-bridge": bridge base (IP Pairing)

- reg: Must contain an entry for each entry in reg-names.

- reset-names: Must include the following entries:

  "pwrap"

  "pwrap-bridge" (IP Pairing)

- resets: Must contain an entry for each entry in reset-names.

- clock-names: Must include the following entries:

  "spi": SPI bus clock

  "wrap": Main module clock

- clocks: Must contain an entry for each entry in clock-names.



Optional properities:

- reset-names: Some SoCs include the following entries:

  "pwrap"

  "pwrap-bridge" (IP Pairing)

- resets: Must contain an entry for each entry in reset-names.

- pmic: Using either MediaTek PMIC MFD as the child device of pwrap

  See the following for child node definitions:

  Documentation/devicetree/bindings/mfd/mt6397.txt

drivers/soc/mediatek/mt8167-mmsys.h

+1 −1
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = { 
		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,

		MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,

	}, {

		DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,

		MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0

	}, {

		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,

drivers/soc/mediatek/mt8183-mmsys.h

+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = { 
		MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,

		MT8183_OVL1_2L_MOUT_EN_RDMA1

	}, {

		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,

		MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,

		MT8183_DITHER0_MOUT_IN_DSI0

	}, {

drivers/soc/mediatek/mt8186-mmsys.h

+2 −2
Original line number Diff line number Diff line
@@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = { 
		MT8186_RDMA0_SOUT_TO_COLOR0

	},

	{

		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,

		MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,

		MT8186_DITHER0_MOUT_TO_DSI0,

	},

	{

		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,

		MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,

		MT8186_DSI0_FROM_DITHER0

	},