Unverified Commit f03877e3 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!11237 CVE-2024-43907 

Merge Pull Request from: @ci-robot 
 
PR sync from: Yongqiang Liu <liuyongqiang13@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/PEE64S4DGWBO7RCAJV7KX5ZZQQ27WXMT/ 
Ma Jun (1):
  drm/amdgpu/pm: Fix the null pointer dereference in
    apply_state_adjust_rules


-- 
2.25.1
 
https://gitee.com/src-openeuler/kernel/issues/IAMMCR 
 
Link:https://gitee.com/openeuler/kernel/pulls/11237

 

Reviewed-by: default avatarYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: default avatarYang Yingliang <yangyingliang@huawei.com>
parents 388ff999 9b75c3be

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

+5 −2
Original line number Diff line number Diff line
@@ -2983,8 +2983,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
			const struct pp_power_state *current_ps)

{

	struct amdgpu_device *adev = hwmgr->adev;

	struct smu7_power_state *smu7_ps =

				cast_phw_smu7_power_state(&request_ps->hardware);

	struct smu7_power_state *smu7_ps;

	uint32_t sclk;

	uint32_t mclk;

	struct PP_Clocks minimum_clocks = {0};
@@ -2998,6 +2997,10 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
	int32_t count;

	int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;



	smu7_ps = cast_phw_smu7_power_state(&request_ps->hardware);

	if (!smu7_ps)

		return -EINVAL;



	data->battery_state = (PP_StateUILabel_Battery ==

			request_ps->classification.ui_label);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

+8 −6
Original line number Diff line number Diff line
@@ -1051,16 +1051,18 @@ static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
				struct pp_power_state  *prequest_ps,

			const struct pp_power_state *pcurrent_ps)

{

	struct smu8_power_state *smu8_ps =

				cast_smu8_power_state(&prequest_ps->hardware);



	const struct smu8_power_state *smu8_current_ps =

				cast_const_smu8_power_state(&pcurrent_ps->hardware);



	struct smu8_power_state *smu8_ps;

	const struct smu8_power_state *smu8_current_ps;

	struct smu8_hwmgr *data = hwmgr->backend;

	struct PP_Clocks clocks = {0, 0, 0, 0};

	bool force_high;



	smu8_ps = cast_smu8_power_state(&prequest_ps->hardware);

	smu8_current_ps = cast_const_smu8_power_state(&pcurrent_ps->hardware);



	if (!smu8_ps || !smu8_current_ps)

		return -EINVAL;



	smu8_ps->need_dfs_bypass = true;



	data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

+5 −2
Original line number Diff line number Diff line
@@ -3232,8 +3232,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
			const struct pp_power_state *current_ps)

{

	struct amdgpu_device *adev = hwmgr->adev;

	struct vega10_power_state *vega10_ps =

				cast_phw_vega10_power_state(&request_ps->hardware);

	struct vega10_power_state *vega10_ps;

	uint32_t sclk;

	uint32_t mclk;

	struct PP_Clocks minimum_clocks = {0};
@@ -3251,6 +3250,10 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
	uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;

	uint32_t latency;



	vega10_ps = cast_phw_vega10_power_state(&request_ps->hardware);

	if (!vega10_ps)

		return -EINVAL;



	data->battery_state = (PP_StateUILabel_Battery ==

			request_ps->classification.ui_label);